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authorGregory CLEMENT <gregory.clement@free-electrons.com>2016-11-05 21:03:50 +0300
committerGregory CLEMENT <gregory.clement@free-electrons.com>2016-11-19 11:16:35 +0300
commit007d05d898050ffc70fd2737896528c5069f7269 (patch)
tree18ebf273fc48790e82a3e1ab14cb02a9bfaffe6c /arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
parent1fc2129553c5a387be786c4b302e3a253a7d01a8 (diff)
downloadlinux-007d05d898050ffc70fd2737896528c5069f7269.tar.xz
ARM: dts: armada-xp: Fixup pcie DT warnings
PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-xp-netgear-rn2120.dts')
-rw-r--r--arch/arm/boot/dts/armada-xp-netgear-rn2120.dts44
1 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index c4685cb86f06..5aaaf0fb2330 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -67,28 +67,6 @@
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
- pcie-controller {
- status = "okay";
-
- /* Connected to first Marvell 88SE9170 SATA controller */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Connected to second Marvell 88SE9170 SATA controller */
- pcie@2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
- };
-
- /* Connected to Fresco Logic FL1009 USB 3.0 controller */
- pcie@5,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
@@ -290,6 +268,28 @@
};
};
+&pciec {
+ status = "okay";
+
+ /* Connected to first Marvell 88SE9170 SATA controller */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Connected to second Marvell 88SE9170 SATA controller */
+ pcie@2,0 {
+ /* Port 0, Lane 1 */
+ status = "okay";
+ };
+
+ /* Connected to Fresco Logic FL1009 USB 3.0 controller */
+ pcie@5,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;