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authorArnaud Ebalard <arno@natisbad.org>2013-10-01 02:19:16 +0400
committerJason Cooper <jason@lakedaemon.net>2013-10-01 04:46:30 +0400
commitb643f85814f69306b9a6e0df34a1c8acb97d3bbd (patch)
tree3271d11a61ad32b0f3a5c9f1ddb9fc62d8f44a78 /arch/arm/boot/dts/armada-370-netgear-rn102.dts
parent2832cf2558095854bcefe5a4e3690f4921f9f3a6 (diff)
downloadlinux-b643f85814f69306b9a6e0df34a1c8acb97d3bbd.tar.xz
ARM: mvebu: add missing DT Mbus ranges and relocate PCIe DT nodes for RN102
When 5e12a613 and 0cd3754a were introduced, Netgear ReadyNAS 102 .dts file was queued for inclusion and missed the update to have Mbus (and then BootROM) ranges properties declared. It also missed the relocation of Armada 370/XP PCIe DT nodes introduced by 14fd8ed0 after de1af8d4. This patch fixes that which makes 3.12-rc3 bootable on the NAS. Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/armada-370-netgear-rn102.dts')
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn102.dts35
1 files changed, 19 insertions, 16 deletions
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 40e73be31720..8ac2ac1f69cc 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -27,6 +27,25 @@
};
soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+ MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+
+ pcie-controller {
+ status = "okay";
+
+ /* Connected to Marvell SATA controller */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /* Connected to FL1009 USB 3.0 controller */
+ pcie@2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+ };
+
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
@@ -94,22 +113,6 @@
pwm_polarity = <0>;
};
};
-
- pcie-controller {
- status = "okay";
-
- /* Connected to Marvell SATA controller */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /* Connected to FL1009 USB 3.0 controller */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
};
};