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authorNoam Camus <noamc@ezchip.com>2015-04-10 21:28:50 +0300
committerVineet Gupta <vgupta@synopsys.com>2016-05-09 07:02:33 +0300
commitb1f2f6f3cf5e37f0418f6cebf365cff7c3abf6d7 (patch)
treed9a8d9d4d37ed7cbe7f098993c3856c756666d18 /arch/arc
parenta5a10d99a946602cf4ae50eadc65c2480dbd2e56 (diff)
downloadlinux-b1f2f6f3cf5e37f0418f6cebf365cff7c3abf6d7.tar.xz
ARC: [plat-eznps] Use dedicated SMP barriers
NPS device got 256 cores and each got 16 HW threads (SMT). We use EZchip dedicated ISA to trigger HW scheduler of the core that current HW thread belongs to. This scheduling makes sure that data beyond barrier is available to all HW threads in core and by that to all in device (4K). Signed-off-by: Noam Camus <noamc@ezchip.com> Cc: Peter Zijlstra <peterz@infradead.org>
Diffstat (limited to 'arch/arc')
-rw-r--r--arch/arc/include/asm/barrier.h12
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/arc/include/asm/barrier.h b/arch/arc/include/asm/barrier.h
index a7209983ee64..b1e327495c7d 100644
--- a/arch/arc/include/asm/barrier.h
+++ b/arch/arc/include/asm/barrier.h
@@ -30,9 +30,7 @@
#define rmb() asm volatile("dmb 1\n" : : : "memory")
#define wmb() asm volatile("dmb 2\n" : : : "memory")
-#endif
-
-#ifdef CONFIG_ISA_ARCOMPACT
+#elif !defined(CONFIG_ARC_PLAT_EZNPS) /* CONFIG_ISA_ARCOMPACT */
/*
* ARCompact based cores (ARC700) only have SYNC instruction which is super
@@ -41,6 +39,14 @@
*/
#define mb() asm volatile("sync\n" : : : "memory")
+
+#else /* CONFIG_ARC_PLAT_EZNPS */
+
+#include <plat/ctop.h>
+
+#define mb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory")
+#define rmb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RD) : "memory")
+
#endif
#include <asm-generic/barrier.h>