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authorIngo Molnar <mingo@kernel.org>2017-11-02 12:57:24 +0300
committerIngo Molnar <mingo@kernel.org>2017-11-02 12:57:24 +0300
commit3357b0d3c7323d73806571192e9f633bb6ba3d54 (patch)
treea92fb225bfdda901783ad662a1fea0baddfb81e1 /arch/arc/plat-hsdk/platform.c
parent82c62fa0c49aa305104013cee4468772799bb391 (diff)
parente27c310af5c05cf876d9cad006928076c27f54d4 (diff)
downloadlinux-3357b0d3c7323d73806571192e9f633bb6ba3d54.tar.xz
Merge branch 'x86/mpx/prep' into x86/asm
Pick up some of the MPX commits that modify the syscall entry code, to have a common base and to reduce conflicts. Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/arc/plat-hsdk/platform.c')
-rw-r--r--arch/arc/plat-hsdk/platform.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arc/plat-hsdk/platform.c b/arch/arc/plat-hsdk/platform.c
index 744e62e58788..fd0ae5e38639 100644
--- a/arch/arc/plat-hsdk/platform.c
+++ b/arch/arc/plat-hsdk/platform.c
@@ -74,6 +74,10 @@ static void __init hsdk_set_cpu_freq_1ghz(void)
pr_err("Failed to setup CPU frequency to 1GHz!");
}
+#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
+#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
+#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
+
static void __init hsdk_init_early(void)
{
/*
@@ -90,6 +94,12 @@ static void __init hsdk_init_early(void)
writel(1, (void __iomem *) CREG_PAE_UPDATE);
/*
+ * Switch SDIO external ciu clock divider from default div-by-8 to
+ * minimum possible div-by-2.
+ */
+ iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
+
+ /*
* Setup CPU frequency to 1GHz.
* TODO: remove it after smart hsdk pll driver will be introduced.
*/