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| author | Thomas Gleixner <tglx@linutronix.de> | 2015-12-19 13:03:18 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2015-12-19 13:03:18 +0300 |
| commit | d267b8d6c65ed7636a412ca479b96df7c0f5b27b (patch) | |
| tree | f613d83fab377bf3599eb9ffc3cdf34df0a6e48e /arch/arc/mm/tlbex.S | |
| parent | 42baa2581c92f8d07e7260506c8d41caf14b0fc3 (diff) | |
| parent | 1eab0e42450c6038e2bb17da438370fe639973f3 (diff) | |
| download | linux-d267b8d6c65ed7636a412ca479b96df7c0f5b27b.tar.xz | |
Merge branch 'linus' into x86/apic
Pull in update changes so we can apply conflicting patches
Diffstat (limited to 'arch/arc/mm/tlbex.S')
| -rw-r--r-- | arch/arc/mm/tlbex.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index 63860adc4814..f1967eeb32e7 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -88,7 +88,7 @@ ex_saved_reg1: #ifdef CONFIG_SMP sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with GET_CPU_ID r0 ; get to per cpu scratch mem, - lsl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu + asl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu add r0, @ex_saved_reg1, r0 #else st r0, [@ex_saved_reg1] @@ -107,7 +107,7 @@ ex_saved_reg1: .macro TLBMISS_RESTORE_REGS #ifdef CONFIG_SMP GET_CPU_ID r0 ; get to per cpu scratch mem - lsl r0, r0, L1_CACHE_SHIFT ; each is cache line wide + asl r0, r0, L1_CACHE_SHIFT ; each is cache line wide add r0, @ex_saved_reg1, r0 ld_s r3, [r0,12] ld_s r2, [r0, 8] @@ -256,7 +256,7 @@ ex_saved_reg1: .macro CONV_PTE_TO_TLB and r3, r0, PTE_BITS_RWX ; r w x - lsl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only) + asl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only) and.f 0, r0, _PAGE_GLOBAL or.z r2, r2, r3 ; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page) |