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authorAndrea Gelmini <andrea.gelmini@gelma.net>2016-05-21 14:45:35 +0300
committerVineet Gupta <vgupta@synopsys.com>2016-05-30 07:37:32 +0300
commit2547476a5e4061f6addb88d5fc837d3a950f54c4 (patch)
tree714716f146f5b1b5ee3b0afd86e4acd658617e76 /arch/arc/include/asm/pgtable.h
parent1a695a905c18548062509178b98bc91e67510864 (diff)
downloadlinux-2547476a5e4061f6addb88d5fc837d3a950f54c4.tar.xz
Fix typos
Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include/asm/pgtable.h')
-rw-r--r--arch/arc/include/asm/pgtable.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 034bbdc0ff61..858f98ef7f1b 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -47,7 +47,7 @@
* Page Tables are purely for Linux VM's consumption and the bits below are
* suited to that (uniqueness). Hence some are not implemented in the TLB and
* some have different value in TLB.
- * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible becoz they live in
+ * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible because they live in
* seperate PD0 and PD1, which combined forms a translation entry)
* while for PTE perspective, they are 8 and 9 respectively
* with MMU v3: Most bits (except SHARED) represent the exact hardware pos