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| author | Vineet Gupta <vgupta@synopsys.com> | 2016-09-29 20:00:14 +0300 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2016-10-17 01:49:07 +0300 |
| commit | 3ce0fefc51bd56381b1b9a92835cf8f9db3f2ef8 (patch) | |
| tree | c425859767f89b65b4d11b41325632ffd82afffb /arch/arc/include/asm/mcip.h | |
| parent | 1001354ca34179f3db924eb66672442a173147dc (diff) | |
| download | linux-3ce0fefc51bd56381b1b9a92835cf8f9db3f2ef8.tar.xz | |
ARCv2: intc: untangle SMP, MCIP and IDU
The IDU intc is technically part of MCIP (Multi-core IP) hence
historically was only available in a SMP hardware build (and thus only
in a SMP kernel build). Now that hardware restriction has been lifted,
so a UP kernel needs to support it.
This requires breaking mcip.c into parts which are strictly SMP
(inter-core interrupts) and IDU which in reality is just another
intc and thus has no bearing on SMP.
This change allows IDU in UP builds and with a suitable device tree, we
can have the cascaded intc system
ARCv2 core intc <---> ARCv2 IDU intc <---> periperals
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include/asm/mcip.h')
| -rw-r--r-- | arch/arc/include/asm/mcip.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arc/include/asm/mcip.h b/arch/arc/include/asm/mcip.h index 847e3bbe387f..c8fbe4114bad 100644 --- a/arch/arc/include/asm/mcip.h +++ b/arch/arc/include/asm/mcip.h @@ -55,6 +55,22 @@ struct mcip_cmd { #define IDU_M_DISTRI_DEST 0x2 }; +struct mcip_bcr { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad3:8, + idu:1, llm:1, num_cores:6, + iocoh:1, gfrc:1, dbg:1, pad2:1, + msg:1, sem:1, ipi:1, pad:1, + ver:8; +#else + unsigned int ver:8, + pad:1, ipi:1, sem:1, msg:1, + pad2:1, dbg:1, gfrc:1, iocoh:1, + num_cores:6, llm:1, idu:1, + pad3:8; +#endif +}; + /* * MCIP programming model * |