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authorVineet Gupta <vgupta@synopsys.com>2015-06-04 12:09:15 +0300
committerVineet Gupta <vgupta@synopsys.com>2015-06-22 11:36:56 +0300
commitbcc4d65abec2adb74157b34519e80331eb4427eb (patch)
treebb35ec4fc31cc6f9e8d3063c82cf682e2e723434 /arch/arc/include/asm/cache.h
parentd1f317d8254413447bcd6b6adbde24a985d256c2 (diff)
downloadlinux-bcc4d65abec2adb74157b34519e80331eb4427eb.tar.xz
ARCv2: MMUv4: support aliasing icache config
This is also default for AXS103 release Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include/asm/cache.h')
-rw-r--r--arch/arc/include/asm/cache.h4
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index e54977a7d006..d21c76d6b054 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -60,7 +60,7 @@ extern void read_decode_cache_bcr(void);
#define ARC_REG_IC_IVIC 0x10
#define ARC_REG_IC_CTRL 0x11
#define ARC_REG_IC_IVIL 0x19
-#if defined(CONFIG_ARC_MMU_V3)
+#if defined(CONFIG_ARC_MMU_V3) || defined(CONFIG_ARC_MMU_V4)
#define ARC_REG_IC_PTAG 0x1E
#endif
@@ -74,9 +74,7 @@ extern void read_decode_cache_bcr(void);
#define ARC_REG_DC_IVDL 0x4A
#define ARC_REG_DC_FLSH 0x4B
#define ARC_REG_DC_FLDL 0x4C
-#if defined(CONFIG_ARC_MMU_V3)
#define ARC_REG_DC_PTAG 0x5C
-#endif
/* Bit val in DC_CTRL */
#define DC_CTRL_INV_MODE_FLUSH 0x40