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authorVineet Gupta <vgupta@synopsys.com>2015-03-11 19:12:37 +0300
committerVineet Gupta <vgupta@synopsys.com>2015-06-25 03:30:17 +0300
commitb8a033023994c4e59697bb3b16b441b38f258390 (patch)
tree2a5524af921d907162b1f476537117a02c02a127 /arch/arc/include/asm/bitops.h
parent470c27e4695add2a4e167467775081870d83185a (diff)
downloadlinux-b8a033023994c4e59697bb3b16b441b38f258390.tar.xz
ARCv2: barriers
ARCv2 based HS38 cores are weakly ordered and thus explicit barriers for kernel proper. SMP barrier is provided by DMB instruction which also guarantees local barrier hence used as backend of smp_*mb() as well as *mb() APIs Also hookup barriers into MMIO accessors to avoid ordering issues in IO Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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