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authorBenjamin Li <benli@broadcom.com>2010-01-08 11:51:21 +0300
committerDavid S. Miller <davem@davemloft.net>2010-01-08 11:51:21 +0300
commite2eb8e38592f28d8be4a518f44d3385272dedddb (patch)
treecdcf465e988219f50d5aff779e0b2d61c462cf5b /README
parent368c0ca2f0a69b0818fbc1796d8e21ff02a61b4c (diff)
downloadlinux-e2eb8e38592f28d8be4a518f44d3385272dedddb.tar.xz
bnx2: Flush the register writes which setup the MSI-X table
The MSI-X table size needs to be properly set before pci_enable_msix() is called. But on certain machines, the writes are delayed and the MSI-X table size is incorrectly read. By reading the BNX2_PCI_MSIX_CONTROL register, the writes are flushed and now ensure that the MSI-X table is set correctly before MSI-X is enable on the device. This patch was originally diagnosed and authored by Kalyan Ram Chintalapati <kalyanc@vmware.com>. Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: Kalyan Ram Chintalapati <kalyanc@vmware.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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