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authorDan Williams <dan.j.williams@intel.com>2022-05-28 06:51:19 +0300
committerDan Williams <dan.j.williams@intel.com>2022-07-22 03:19:24 +0300
commit391785859e7e6521f622ad8c965c9792767023bc (patch)
treeebbdac616cd6b926d65dccbb3357e5b89091e4ad /LICENSES
parent256d0e9ee4f2f14d30b93fd593cef3108b0527ca (diff)
downloadlinux-391785859e7e6521f622ad8c965c9792767023bc.tar.xz
cxl/port: Move dport tracking to an xarray
Reduce the complexity and the overhead of walking the topology to determine endpoint connectivity to root decoder interleave configurations. Note that cxl_detach_ep(), after it determines that the last @ep has departed and decides to delete the port, now needs to walk the dport array with the device_lock() held to remove entries. Previously list_splice_init() could be used atomically delete all dport entries at once and then perform entry tear down outside the lock. There is no list_splice_init() equivalent for the xarray. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/165784331647.1758207.6345820282285119339.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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