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authorIvan Bornyakov <i.bornyakov@metrotek.ru>2022-06-23 19:32:47 +0300
committerXu Yilun <yilun.xu@intel.com>2022-06-24 07:12:38 +0300
commitb7eb6da9b5f9c8cee231e466e107acdd5e5d2909 (patch)
treec40886f9d4b6a5315c1c4cd3491cdca6dac652d1 /Documentation
parent5f8d4a9008307e0bf210906948953386935d361c (diff)
downloadlinux-b7eb6da9b5f9c8cee231e466e107acdd5e5d2909.tar.xz
dt-bindings: fpga: add binding doc for microchip-spi fpga mgr
Add Device Tree Binding doc for Microchip Polarfire FPGA Manager using slave SPI to load .dat formatted bitstream image. Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Xu Yilun <yilun.xu@intel.com> Link: https://lore.kernel.org/r/20220623163248.3672-5-i.bornyakov@metrotek.ru Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml44
1 files changed, 44 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
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index 000000000000..aee45cb15592
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Polarfire FPGA manager.
+
+maintainers:
+ - Ivan Bornyakov <i.bornyakov@metrotek.ru>
+
+description:
+ Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
+ load the bitstream in .dat format.
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpf-spi-fpga-mgr
+
+ reg:
+ description: SPI chip select
+ maxItems: 1
+
+ spi-max-frequency: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga_mgr@0 {
+ compatible = "microchip,mpf-spi-fpga-mgr";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+ };