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| author | Michael Walle <michael@walle.cc> | 2022-03-18 23:13:22 +0300 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2022-03-22 08:33:01 +0300 |
| commit | a2e4b5adfdf85d4a94af8a7a9f44e3ee254fd77e (patch) | |
| tree | 60fbacdbc03beaf56ff7c5f89bf1e2facd2cfeb4 /Documentation | |
| parent | c050f5e91b47f8f5ae67b9158afd66f8be48f3dc (diff) | |
| download | linux-a2e4b5adfdf85d4a94af8a7a9f44e3ee254fd77e.tar.xz | |
dt-bindings: net: mscc-miim: add lan966x compatible
The MDIO controller has support to release the internal PHYs from reset
by specifying a second memory resource. This is different between the
currently supported SparX-5 and the LAN966x. Add a new compatible to
distinguish between these two.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/net/mscc-miim.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/net/mscc-miim.txt b/Documentation/devicetree/bindings/net/mscc-miim.txt index 7104679cf59d..70e0cb1ee485 100644 --- a/Documentation/devicetree/bindings/net/mscc-miim.txt +++ b/Documentation/devicetree/bindings/net/mscc-miim.txt @@ -2,7 +2,7 @@ Microsemi MII Management Controller (MIIM) / MDIO ================================================= Properties: -- compatible: must be "mscc,ocelot-miim" +- compatible: must be "mscc,ocelot-miim" or "microchip,lan966x-miim" - reg: The base address of the MDIO bus controller register bank. Optionally, a second register bank can be defined if there is an associated reset register for internal PHYs |