Merge branch 'remotes/lorenzo/pci/mvebu'

- Add Pali Rohár as pci-mvebu.c maintainer (Pali Rohár)

- Make struct pci_bridge_emul_ops const (Pali Rohár)

- Rename PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR to
  PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD since it doesn't apply to BARs (Pali
  Rohár)

- Add new flag PCI_BRIDGE_EMUL_NO_IO_FORWARD for bridges that don't support
  IO forwarding (Pali Rohár)

- Add Kconfig help text for CONFIG_PCI_MVEBU (Pali Rohár)

- Remove duplicate nports assignment (Pali Rohár)

- Set PCI_BRIDGE_EMUL_NO_IO_FORWARD when IO is unsupported (Pali Rohár)

- Initialize vendor, device and revision of emulated bridge (Pali Rohár)

- Fix Data Link Layer Link Active reporting on emulated bridge (Pali Rohár)

- Rearrange tests in bridge emulation for easier maintenance (Russell King)

- Add emulated bridge support for PCIe extended capabilities (Russell King)

- Add emulated bridge support for bridge Subsystem Vendor ID capability
  (Pali Rohár)

- Configure Maximum Link Width based on DT "num-lanes" property (Pali
  Rohár)

- Emulate bridge Subsystem Vendor ID capability (Pali Rohár)

- Emulate AER Capability (Pali Rohár)

- Use PCI core bridge->ops and bridge->child_ops to separate config
  accesses to Root Port vs downstream devices (Pali Rohár)

- Unmask all INTx interrupts; they're reported via a single shared GIC
  source (Pali Rohár)

- Add INTx support (Pali Rohár)

* remotes/lorenzo/pci/mvebu:
  PCI: mvebu: Implement support for legacy INTx interrupts
  PCI: mvebu: Fix macro names and comments about legacy interrupts
  dt-bindings: PCI: mvebu: Update information about intx interrupts
  PCI: mvebu: Use child_ops API
  PCI: mvebu: Add support for Advanced Error Reporting registers on emulated bridge
  PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge
  PCI: mvebu: Correctly configure x1/x4 mode
  dt-bindings: PCI: mvebu: Add num-lanes property
  PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability
  PCI: pci-bridge-emul: Add support for PCIe extended capabilities
  PCI: pci-bridge-emul: Re-arrange register tests
  PCI: mvebu: Fix reporting Data Link Layer Link Active on emulated bridge
  PCI: mvebu: Update comment for PCI_EXP_LNKCTL register on emulated bridge
  PCI: mvebu: Update comment for PCI_EXP_LNKCAP register on emulated bridge
  PCI: mvebu: Properly initialize vendor, device and revision of emulated bridge
  PCI: mvebu: Set PCI_BRIDGE_EMUL_NO_IO_FORWARD when IO is unsupported
  PCI: mvebu: Remove duplicate nports assignment
  PCI: mvebu: Add help string for CONFIG_PCI_MVEBU option
  PCI: pci-bridge-emul: Add support for new flag PCI_BRIDGE_EMUL_NO_IO_FORWARD
  PCI: pci-bridge-emul: Rename PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR to PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD
  PCI: pci-bridge-emul: Make struct pci_bridge_emul_ops as const
  MAINTAINERS: Add Pali Rohár as pci-mvebu.c maintainer

1 files changed, 16 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
index 6173af6885f8..6d022a9d36ee 100644
--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
@@ -77,9 +77,15 @@ and the following optional properties:
 - marvell,pcie-lane: the physical PCIe lane number, for ports having
   multiple lanes. If this property is not found, we assume that the
   value is 0.
+- num-lanes: number of SerDes PCIe lanes for this link (1 or 4)
 - reset-gpios: optional GPIO to PERST#
 - reset-delay-us: delay in us to wait after reset de-assertion, if not
   specified will default to 100ms, as required by the PCIe specification.
+- interrupt-names: list of interrupt names, supported are:
+   - "intx" - interrupt line triggered by one of the legacy interrupt
+- interrupts or interrupts-extended: List of the interrupt sources which
+  corresponding to the "interrupt-names". If non-empty then also additional
+  'interrupt-controller' subnode must be defined.
 
 Example:
 
@@ -141,6 +147,7 @@ pcie-controller {
 		interrupt-map = <0 0 0 0 &mpic 58>;
 		marvell,pcie-port = <0>;
 		marvell,pcie-lane = <0>;
+		num-lanes = <1>;
 		/* low-active PERST# reset on GPIO 25 */
 		reset-gpios = <&gpio0 25 1>;
 		/* wait 20ms for device settle after reset deassertion */
@@ -161,6 +168,7 @@ pcie-controller {
 		interrupt-map = <0 0 0 0 &mpic 59>;
 		marvell,pcie-port = <0>;
 		marvell,pcie-lane = <1>;
+		num-lanes = <1>;
 		clocks = <&gateclk 6>;
 	};
 
@@ -177,6 +185,7 @@ pcie-controller {
 		interrupt-map = <0 0 0 0 &mpic 60>;
 		marvell,pcie-port = <0>;
 		marvell,pcie-lane = <2>;
+		num-lanes = <1>;
 		clocks = <&gateclk 7>;
 	};
 
@@ -193,6 +202,7 @@ pcie-controller {
 		interrupt-map = <0 0 0 0 &mpic 61>;
 		marvell,pcie-port = <0>;
 		marvell,pcie-lane = <3>;
+		num-lanes = <1>;
 		clocks = <&gateclk 8>;
 	};
 
@@ -209,6 +219,7 @@ pcie-controller {
 		interrupt-map = <0 0 0 0 &mpic 62>;
 		marvell,pcie-port = <1>;
 		marvell,pcie-lane = <0>;
+		num-lanes = <1>;
 		clocks = <&gateclk 9>;
 	};
 
@@ -225,6 +236,7 @@ pcie-controller {
 		interrupt-map = <0 0 0 0 &mpic 63>;
 		marvell,pcie-port = <1>;
 		marvell,pcie-lane = <1>;
+		num-lanes = <1>;
 		clocks = <&gateclk 10>;
 	};
 
@@ -241,6 +253,7 @@ pcie-controller {
 		interrupt-map = <0 0 0 0 &mpic 64>;
 		marvell,pcie-port = <1>;
 		marvell,pcie-lane = <2>;
+		num-lanes = <1>;
 		clocks = <&gateclk 11>;
 	};
 
@@ -257,6 +270,7 @@ pcie-controller {
 		interrupt-map = <0 0 0 0 &mpic 65>;
 		marvell,pcie-port = <1>;
 		marvell,pcie-lane = <3>;
+		num-lanes = <1>;
 		clocks = <&gateclk 12>;
 	};
 
@@ -273,6 +287,7 @@ pcie-controller {
 		interrupt-map = <0 0 0 0 &mpic 99>;
 		marvell,pcie-port = <2>;
 		marvell,pcie-lane = <0>;
+		num-lanes = <1>;
 		clocks = <&gateclk 26>;
 	};
 
@@ -289,6 +304,7 @@ pcie-controller {
 		interrupt-map = <0 0 0 0 &mpic 103>;
 		marvell,pcie-port = <3>;
 		marvell,pcie-lane = <0>;
+		num-lanes = <1>;
 		clocks = <&gateclk 27>;
 	};
 };