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authorLinus Torvalds <torvalds@linux-foundation.org>2018-06-07 23:35:59 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2018-06-07 23:35:59 +0300
commit3a979e8c07e3ee9933016368db0a55943b00a089 (patch)
treeae736c374725c2c2ef1ee2e01ba44a1dd7026a30 /Documentation
parenta1cdde8c411dbde19863e5104a4a1f218dd07b89 (diff)
parentf83d1cfc8bcddf93bb6f55940fd59f5b047863e5 (diff)
downloadlinux-3a979e8c07e3ee9933016368db0a55943b00a089.tar.xz
Merge tag 'mailbox-v4.18' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar: - Remove HAS_DMA config dependencies - New STMicroelectronics STM32 IPCC driver - Enable QCom driver to run more controllers - Fixed return code from null to ptr-err for Brcm driver - Fix kconfig dependencies for the HiSilicon driver * tag 'mailbox-v4.18' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox/drivers/hisi: Consolidate the Kconfig for the MAILBOX mailbox: Add support for Qualcomm SDM845 SoCs dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs mailbox: bcm2835: Fix of_xlate return value mailbox: qcom: Add msm8998 hmss compatible mailbox: add STMicroelectronics STM32 IPCC driver dt-bindings: mailbox: add STMicroelectronics STM32 IPCC binding mailbox: Remove depends on HAS_DMA in case of platform dependency
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt2
-rw-r--r--Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt47
2 files changed, 49 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
index 16964f0c1773..6e8a9ab0fdae 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
@@ -10,6 +10,8 @@ platforms.
Definition: must be one of:
"qcom,msm8916-apcs-kpss-global",
"qcom,msm8996-apcs-hmss-global"
+ "qcom,msm8998-apcs-hmss-global"
+ "qcom,sdm845-apss-shared"
- reg:
Usage: required
diff --git a/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt b/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt
new file mode 100644
index 000000000000..1d2b7fee7b85
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt
@@ -0,0 +1,47 @@
+* STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller)
+
+The IPCC block provides a non blocking signaling mechanism to post and
+retrieve messages in an atomic way between two processors.
+It provides the signaling for N bidirectionnal channels. The number of channels
+(N) can be read from a dedicated register.
+
+Required properties:
+- compatible: Must be "st,stm32mp1-ipcc"
+- reg: Register address range (base address and length)
+- st,proc-id: Processor id using the mailbox (0 or 1)
+- clocks: Input clock
+- interrupt-names: List of names for the interrupts described by the interrupt
+ property. Must contain the following entries:
+ - "rx"
+ - "tx"
+ - "wakeup"
+- interrupts: Interrupt specifiers for "rx channel occupied", "tx channel
+ free" and "system wakeup".
+- #mbox-cells: Number of cells required for the mailbox specifier. Must be 1.
+ The data contained in the mbox specifier of the "mboxes"
+ property in the client node is the mailbox channel index.
+
+Optional properties:
+- wakeup-source: Flag to indicate whether this device can wake up the system
+
+
+
+Example:
+ ipcc: mailbox@4c001000 {
+ compatible = "st,stm32mp1-ipcc";
+ #mbox-cells = <1>;
+ reg = <0x4c001000 0x400>;
+ st,proc-id = <0>;
+ interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>,
+ <&intc GIC_SPI 101 IRQ_TYPE_NONE>,
+ <&aiec 62 1>;
+ interrupt-names = "rx", "tx", "wakeup";
+ clocks = <&rcc_clk IPCC>;
+ wakeup-source;
+ }
+
+Client:
+ mbox_test {
+ ...
+ mboxes = <&ipcc 0>, <&ipcc 1>;
+ };