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| author | Anshuman Khandual <anshuman.khandual@arm.com> | 2023-09-21 06:36:31 +0300 |
|---|---|---|
| committer | Suzuki K Poulose <suzuki.poulose@arm.com> | 2023-11-16 14:35:09 +0300 |
| commit | e5d207b24c54af25fb763af44e2db35347a0f7ee (patch) | |
| tree | 3ed501d0837740011ab9a9eb9dc1a262bfe0c3e6 /Documentation/trace | |
| parent | 94566c5b07744c7cf5c7cc0ad42b15996ba0b054 (diff) | |
| download | linux-e5d207b24c54af25fb763af44e2db35347a0f7ee.tar.xz | |
Documentation: coresight: Add cc_threshold tunable
This updates config option to include 'cc_threshold' tunable value.
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: James Clark <james.clark@arm.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Reviewed by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230921033631.1298723-4-anshuman.khandual@arm.com
Diffstat (limited to 'Documentation/trace')
| -rw-r--r-- | Documentation/trace/coresight/coresight.rst | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst index 826e59a698da..d4f93d6a2d63 100644 --- a/Documentation/trace/coresight/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -624,6 +624,10 @@ They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/ * - timestamp - Session local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP <coresight-timestamp>` + * - cc_threshold + - Cycle count threshold value. If nothing is provided here or the provided value is 0, then the + default value i.e 0x100 will be used. If provided value is less than minimum cycles threshold + value, as indicated via TRCIDR3.CCITMIN, then the minimum value will be used instead. How to use the STM module ------------------------- |