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| author | Tianfei zhang <tianfei.zhang@intel.com> | 2022-04-19 06:29:42 +0300 |
|---|---|---|
| committer | Xu Yilun <yilun.xu@intel.com> | 2022-05-10 11:05:27 +0300 |
| commit | 2b28c9e0fe97fa2bae2ab52540a2970c0d3bdf8d (patch) | |
| tree | 0d17b3f1c944949d89511d0fc681b4be0472ae4b /Documentation/fpga/dfl.rst | |
| parent | 88b3f3ff38d188e3c54603ea0244139cc55348fc (diff) | |
| download | linux-2b28c9e0fe97fa2bae2ab52540a2970c0d3bdf8d.tar.xz | |
Documentation: fpga: dfl: add link address of feature id table
This patch adds the link address of feature id table in documentation.
Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
Acked-by: Wu Hao <hao.wu@intel.com>
Link: https://lore.kernel.org/r/20220419032942.427429-3-tianfei.zhang@intel.com
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Diffstat (limited to 'Documentation/fpga/dfl.rst')
| -rw-r--r-- | Documentation/fpga/dfl.rst | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ef9eec71f6f3..15b670926084 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id. FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. +Please refer to below link to existing feature id table and guide for new feature +ids application. +https://github.com/OPAE/dfl-feature-id + + Location of DFLs on a PCI Device ================================ The original method for finding a DFL on a PCI device assumed the start of the |