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authorSteve Shih <sshih@cisco.com>2016-10-17 19:51:05 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-10-27 17:41:56 +0300
commitecb988a3b7985913d1f0112f66667cdd15e40711 (patch)
treed06aea62155b4bc3bc4415f569b2b19f76991416 /Documentation/features
parent32b2921e6a7461fe63b71217067a6cf4bddb132f (diff)
downloadlinux-ecb988a3b7985913d1f0112f66667cdd15e40711.tar.xz
tty: serial: 8250: 8250_core: NXP SC16C2552 workaround
NXP SC16C2552 requires that we always write a reset to the RX FIFO and TX FIFO whenever we enable the FIFOs Cc: xe-kernel@external.cisco.com Signed-off-by: Steve Shih <sshih@cisco.com> Signed-off-by: David Singleton <davsingl@cisco.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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