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authorPeng Fan <peng.fan@nxp.com>2019-09-09 06:39:50 +0300
committerStephen Boyd <sboyd@kernel.org>2019-09-18 08:53:34 +0300
commit60a8a148b2fb494981ba07474d1828d450053225 (patch)
tree70abdbf5ba143bc8e77771085d6319ca57a36b09 /Documentation/driver-api/device_link.rst
parent67315be33e9c04c589fb16a291477bb3983d4283 (diff)
downloadlinux-60a8a148b2fb494981ba07474d1828d450053225.tar.xz
clk: imx: imx8mn: fix pll mux bit
pll BYPASS bit should be kept inside pll driver for glitchless freq setting following spec. If exposing the bit, that means pll driver and clk driver has two paths to touch this bit, which is wrong. So use EXT_BYPASS bit here. And drop uneeded set parent, because EXT_BYPASS default is 0. Suggested-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lkml.kernel.org/r/1568043491-20680-5-git-send-email-peng.fan@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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