Merge branches 'clk-microchip', 'clk-si', 'clk-mtk', 'clk-at91' and 'clk-st' into clk-next

 - Clock configuration on Microchip PolarFire SoCs
 - Free allocations on probe error in Mediatek clk driver
 - Modernize Mediatek clk driver by consolidating code

* clk-microchip:
  clk: microchip: Add driver for Microchip PolarFire SoC
  dt-bindings: clk: microchip: Add Microchip PolarFire host binding

* clk-si:
  clk-si5341: replace snprintf in show functions with sysfs_emit
  clk: si5341: fix reported clk_rate when output divider is 2

* clk-mtk: (32 commits)
  clk: mediatek: Warn if clk IDs are duplicated
  clk: mediatek: mt8195: Implement remove functions
  clk: mediatek: mt8195: Implement error handling in probe functions
  clk: mediatek: mt8195: Hook up mtk_clk_simple_remove()
  clk: mediatek: Unregister clks in mtk_clk_simple_probe() error path
  clk: mediatek: mtk: Implement error handling in register APIs
  clk: mediatek: pll: Implement error handling in register API
  clk: mediatek: mux: Implement error handling in register API
  clk: mediatek: mux: Reverse check for existing clk to reduce nesting level
  clk: mediatek: gate: Implement error handling in register API
  clk: mediatek: cpumux: Implement error handling in register API
  clk: mediatek: mtk: Clean up included headers
  clk: mediatek: Add mtk_clk_simple_remove()
  clk: mediatek: Implement mtk_clk_unregister_composites() API
  clk: mediatek: Implement mtk_clk_unregister_divider_clks() API
  clk: mediatek: Implement mtk_clk_unregister_factors() API
  clk: mediatek: Implement mtk_clk_unregister_fixed_clks() API
  clk: mediatek: pll: Clean up included headers
  clk: mediatek: pll: Implement unregister API
  clk: mediatek: pll: Split definitions into separate header file
  ...

* clk-at91:
  clk: at91: clk-master: remove dead code
  clk: at91: sama7g5: fix parents of PDMCs' GCLK
  clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DT
  clk: at91: allow setting PMC_AUDIOPINCK clock parents via DT

* clk-st:
  clk: stm32mp1: Add parent_data to ETHRX clock
  clk: stm32mp1: Split ETHCK_K into separate MUX and GATE clock