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authorLinus Torvalds <torvalds@linux-foundation.org>2022-03-29 21:06:55 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2022-03-29 21:06:55 +0300
commit1d59c3b669faddb91737f4e59c09305878a971d8 (patch)
treedc00847bb3bd096d95349729d2175a5e8770da68 /Documentation/devicetree
parent5efabdadcf4a5b9a37847ecc85ba71cf2eff0fcf (diff)
parent3b65dd5be3c72b9d2013bfe6e9261e2b06222fa9 (diff)
downloadlinux-1d59c3b669faddb91737f4e59c09305878a971d8.tar.xz
Merge tag 'pm-5.18-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull more power management updates from Rafael Wysocki: "These update ARM cpufreq drivers, the OPP (Operating Performance Points) library and the power management documentation. Specifics: - Add per core DVFS support for QCom SoC (Bjorn Andersson), convert to yaml binding (Manivannan Sadhasivam) and various other fixes to the QCom drivers (Luca Weiss). - Add OPP table for imx7s SoC (Denys Drozdov) and minor fixes (Stefan Agner). - Fix CPPC driver's freq/performance conversions (Pierre Gondois). - Minor generic cleanups (Yury Norov). - Introduce opp-microwatt property to the OPP core, bindings, etc (Lukasz Luba). - Convert DT bindings to schema format and various related fixes (Yassine Oudjana). - Expose OPP's OF node in debugfs (Viresh Kumar). - Add Intel uncore frequency scaling documentation file to its MAINTAINERS entry (Srinivas Pandruvada). - Clean up the AMD P-state driver documentation (Jan Engelhardt)" * tag 'pm-5.18-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (24 commits) Documentation: amd-pstate: grammar and sentence structure updates dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings dt-bindings: dvfs: Use MediaTek CPUFREQ HW as an example Documentation: EM: Describe new registration method using DT OPP: Add support of "opp-microwatt" for EM registration PM: EM: add macro to set .active_power() callback conditionally OPP: Add "opp-microwatt" supporting code dt-bindings: opp: Add "opp-microwatt" entry in the OPP MAINTAINERS: Add additional file to uncore frequency control cpufreq: blocklist Qualcomm sc8280xp and sa8540p in cpufreq-dt-platdev cpufreq: qcom-hw: Add support for per-core-dcvs dt-bindings: power: avs: qcom,cpr: Convert to DT schema arm64: dts: qcom: qcs404: Rename CPU and CPR OPP tables arm64: dts: qcom: msm8996: Rename cluster OPP tables dt-bindings: opp: Convert qcom-nvmem-cpufreq to DT schema dt-bindings: opp: qcom-opp: Convert to DT schema arm64: dts: qcom: msm8996-mtp: Add msm8996 compatible dt-bindings: arm: qcom: Add msm8996 and apq8096 compatibles opp: Expose of-node's name in debugfs cpufreq: CPPC: Fix performance/frequency conversion ...
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt172
-rw-r--r--Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml201
-rw-r--r--Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml166
-rw-r--r--Documentation/devicetree/bindings/dvfs/performance-domain.yaml14
-rw-r--r--Documentation/devicetree/bindings/opp/opp-v2-base.yaml23
-rw-r--r--Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml257
-rw-r--r--Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml60
-rw-r--r--Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt796
-rw-r--r--Documentation/devicetree/bindings/opp/qcom-opp.txt19
-rw-r--r--Documentation/devicetree/bindings/power/avs/qcom,cpr.txt130
-rw-r--r--Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml160
11 files changed, 877 insertions, 1121 deletions
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
deleted file mode 100644
index 9299028ee712..000000000000
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
+++ /dev/null
@@ -1,172 +0,0 @@
-Qualcomm Technologies, Inc. CPUFREQ Bindings
-
-CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
-SoCs to manage frequency in hardware. It is capable of controlling frequency
-for multiple clusters.
-
-Properties:
-- compatible
- Usage: required
- Value type: <string>
- Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
-
-- clocks
- Usage: required
- Value type: <phandle> From common clock binding.
- Definition: clock handle for XO clock and GPLL0 clock.
-
-- clock-names
- Usage: required
- Value type: <string> From common clock binding.
- Definition: must be "xo", "alternate".
-
-- reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Addresses and sizes for the memory of the HW bases in
- each frequency domain.
-- reg-names
- Usage: Optional
- Value type: <string>
- Definition: Frequency domain name i.e.
- "freq-domain0", "freq-domain1".
-
-- #freq-domain-cells:
- Usage: required.
- Definition: Number of cells in a freqency domain specifier.
-
-* Property qcom,freq-domain
-Devices supporting freq-domain must set their "qcom,freq-domain" property with
-phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.
-
-
-Example:
-
-Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch
-DCVS state together.
-
-/ {
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- CPU0: cpu@0 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x0>;
- enable-method = "psci";
- next-level-cache = <&L2_0>;
- qcom,freq-domain = <&cpufreq_hw 0>;
- L2_0: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- L3_0: l3-cache {
- compatible = "cache";
- };
- };
- };
-
- CPU1: cpu@100 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x100>;
- enable-method = "psci";
- next-level-cache = <&L2_100>;
- qcom,freq-domain = <&cpufreq_hw 0>;
- L2_100: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
-
- CPU2: cpu@200 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x200>;
- enable-method = "psci";
- next-level-cache = <&L2_200>;
- qcom,freq-domain = <&cpufreq_hw 0>;
- L2_200: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
-
- CPU3: cpu@300 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x300>;
- enable-method = "psci";
- next-level-cache = <&L2_300>;
- qcom,freq-domain = <&cpufreq_hw 0>;
- L2_300: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
-
- CPU4: cpu@400 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x400>;
- enable-method = "psci";
- next-level-cache = <&L2_400>;
- qcom,freq-domain = <&cpufreq_hw 1>;
- L2_400: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
-
- CPU5: cpu@500 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x500>;
- enable-method = "psci";
- next-level-cache = <&L2_500>;
- qcom,freq-domain = <&cpufreq_hw 1>;
- L2_500: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
-
- CPU6: cpu@600 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x600>;
- enable-method = "psci";
- next-level-cache = <&L2_600>;
- qcom,freq-domain = <&cpufreq_hw 1>;
- L2_600: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
-
- CPU7: cpu@700 {
- device_type = "cpu";
- compatible = "qcom,kryo385";
- reg = <0x0 0x700>;
- enable-method = "psci";
- next-level-cache = <&L2_700>;
- qcom,freq-domain = <&cpufreq_hw 1>;
- L2_700: l2-cache {
- compatible = "cache";
- next-level-cache = <&L3_0>;
- };
- };
- };
-
- soc {
- cpufreq_hw: cpufreq@17d43000 {
- compatible = "qcom,cpufreq-hw";
- reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
- reg-names = "freq-domain0", "freq-domain1";
-
- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
- clock-names = "xo", "alternate";
-
- #freq-domain-cells = <1>;
- };
-}
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
new file mode 100644
index 000000000000..2f1b8b6852a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -0,0 +1,201 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. CPUFREQ
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description: |
+
+ CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
+ SoCs to manage frequency in hardware. It is capable of controlling frequency
+ for multiple clusters.
+
+properties:
+ compatible:
+ oneOf:
+ - description: v1 of CPUFREQ HW
+ items:
+ - const: qcom,cpufreq-hw
+
+ - description: v2 of CPUFREQ HW (EPSS)
+ items:
+ - enum:
+ - qcom,sm8250-cpufreq-epss
+ - const: qcom,cpufreq-epss
+
+ reg:
+ minItems: 2
+ items:
+ - description: Frequency domain 0 register region
+ - description: Frequency domain 1 register region
+ - description: Frequency domain 2 register region
+
+ reg-names:
+ minItems: 2
+ items:
+ - const: freq-domain0
+ - const: freq-domain1
+ - const: freq-domain2
+
+ clocks:
+ items:
+ - description: XO Clock
+ - description: GPLL0 Clock
+
+ clock-names:
+ items:
+ - const: xo
+ - const: alternate
+
+ '#freq-domain-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#freq-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
+ // switch DCVS state together.
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_100>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_200>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_300>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&L2_400>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&L2_500>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ L2_500: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ next-level-cache = <&L2_600>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ L2_600: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ next-level-cache = <&L2_700>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ L2_700: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpufreq@17d43000 {
+ compatible = "qcom,cpufreq-hw";
+ reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
+ reg-names = "freq-domain0", "freq-domain1";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #freq-domain-cells = <1>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
new file mode 100644
index 000000000000..a9a776da5505
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. NVMEM CPUFreq bindings
+
+maintainers:
+ - Ilia Lin <ilia.lin@kernel.org>
+
+description: |
+ In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply
+ voltage is dynamically configured by Core Power Reduction (CPR) depending on
+ current CPU frequency and efuse values.
+ CPR provides a power domain with multiple levels that are selected depending
+ on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
+ according to the required OPPs defined in the CPU OPP tables.
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcs404
+ required:
+ - compatible
+
+properties:
+ cpus:
+ type: object
+
+ patternProperties:
+ 'cpu@[0-9a-f]+':
+ type: object
+
+ properties:
+ power-domains:
+ maxItems: 1
+
+ power-domain-names:
+ items:
+ - const: cpr
+
+ required:
+ - power-domains
+ - power-domain-names
+
+patternProperties:
+ '^opp-table(-[a-z0-9]+)?$':
+ if:
+ properties:
+ compatible:
+ const: operating-points-v2-kryo-cpu
+ then:
+ patternProperties:
+ '^opp-?[0-9]+$':
+ required:
+ - required-opps
+
+additionalProperties: true
+
+examples:
+ - |
+ / {
+ model = "Qualcomm Technologies, Inc. QCS404";
+ compatible = "qcom,qcs404";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ power-domains = <&cpr>;
+ power-domain-names = "cpr";
+ };
+
+ CPU1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ power-domains = <&cpr>;
+ power-domain-names = "cpr";
+ };
+
+ CPU2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x102>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ power-domains = <&cpr>;
+ power-domain-names = "cpr";
+ };
+
+ CPU3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x103>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ power-domains = <&cpr>;
+ power-domain-names = "cpr";
+ };
+ };
+
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2-kryo-cpu";
+ opp-shared;
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ required-opps = <&cpr_opp1>;
+ };
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ required-opps = <&cpr_opp2>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ required-opps = <&cpr_opp3>;
+ };
+ };
+
+ cpr_opp_table: opp-table-cpr {
+ compatible = "operating-points-v2-qcom-level";
+
+ cpr_opp1: opp1 {
+ opp-level = <1>;
+ qcom,opp-fuse-level = <1>;
+ };
+ cpr_opp2: opp2 {
+ opp-level = <2>;
+ qcom,opp-fuse-level = <2>;
+ };
+ cpr_opp3: opp3 {
+ opp-level = <3>;
+ qcom,opp-fuse-level = <3>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml
index 7959d40ded5a..1dcb85a02a76 100644
--- a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml
+++ b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml
@@ -51,10 +51,16 @@ additionalProperties: true
examples:
- |
- performance: performance-controller@12340000 {
- compatible = "qcom,cpufreq-hw";
- reg = <0x12340000 0x1000>;
- #performance-domain-cells = <1>;
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ performance: performance-controller@11bc00 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+
+ #performance-domain-cells = <1>;
+ };
};
// The node above defines a performance controller that is a performance
diff --git a/Documentation/devicetree/bindings/opp/opp-v2-base.yaml b/Documentation/devicetree/bindings/opp/opp-v2-base.yaml
index da0f09eedc0c..76c8acd981b3 100644
--- a/Documentation/devicetree/bindings/opp/opp-v2-base.yaml
+++ b/Documentation/devicetree/bindings/opp/opp-v2-base.yaml
@@ -93,6 +93,21 @@ patternProperties:
minItems: 1
maxItems: 8 # Should be enough regulators
+ opp-microwatt:
+ description: |
+ The power for the OPP in micro-Watts.
+
+ Entries for multiple regulators shall be provided in the same field
+ separated by angular brackets <>. If current values aren't required
+ for a regulator, then it shall be filled with 0. If power values
+ aren't required for any of the regulators, then this field is not
+ required. The OPP binding doesn't provide any provisions to relate the
+ values to their power supplies or the order in which the supplies need
+ to be configured and that is left for the implementation specific
+ binding.
+ minItems: 1
+ maxItems: 8 # Should be enough regulators
+
opp-level:
description:
A value representing the performance level of the device.
@@ -205,6 +220,14 @@ patternProperties:
minItems: 1
maxItems: 8 # Should be enough regulators
+ '^opp-microwatt':
+ description:
+ Named opp-microwatt property. Similar to opp-microamp property,
+ but for microwatt instead.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 8 # Should be enough regulators
+
dependencies:
opp-avg-kBps: [ opp-peak-kBps ]
diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
new file mode 100644
index 000000000000..8c2e9ac5f68d
--- /dev/null
+++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
@@ -0,0 +1,257 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. NVMEM OPP bindings
+
+maintainers:
+ - Ilia Lin <ilia.lin@kernel.org>
+
+allOf:
+ - $ref: opp-v2-base.yaml#
+
+description: |
+ In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996,
+ the CPU frequencies subset and voltage value of each OPP varies based on
+ the silicon variant in use.
+ Qualcomm Technologies, Inc. Process Voltage Scaling Tables
+ defines the voltage and frequency value based on the msm-id in SMEM
+ and speedbin blown in the efuse combination.
+ The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
+ to provide the OPP framework with required information (existing HW bitmap).
+ This is used to determine the voltage and frequency value for each OPP of
+ operating-points-v2 table when it is parsed by the OPP framework.
+
+properties:
+ compatible:
+ const: operating-points-v2-kryo-cpu
+
+ nvmem-cells:
+ description: |
+ A phandle pointing to a nvmem-cells node representing the
+ efuse registers that has information about the
+ speedbin that is used to select the right frequency/voltage
+ value pair.
+
+ opp-shared: true
+
+patternProperties:
+ '^opp-?[0-9]+$':
+ type: object
+
+ properties:
+ opp-hz: true
+
+ opp-microvolt: true
+
+ opp-supported-hw:
+ description: |
+ A single 32 bit bitmap value, representing compatible HW.
+ Bitmap:
+ 0: MSM8996 V3, speedbin 0
+ 1: MSM8996 V3, speedbin 1
+ 2: MSM8996 V3, speedbin 2
+ 3: unused
+ 4: MSM8996 SG, speedbin 0
+ 5: MSM8996 SG, speedbin 1
+ 6: MSM8996 SG, speedbin 2
+ 7-31: unused
+ maximum: 0x77
+
+ clock-latency-ns: true
+
+ required-opps: true
+
+ required:
+ - opp-hz
+
+required:
+ - compatible
+
+if:
+ required:
+ - nvmem-cells
+then:
+ patternProperties:
+ '^opp-?[0-9]+$':
+ required:
+ - opp-supported-hw
+
+additionalProperties: false
+
+examples:
+ - |
+ / {
+ model = "Qualcomm Technologies, Inc. DB820c";
+ compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU2: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU3: cpu@101 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_1>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU2>;
+ };
+
+ core1 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+ };
+
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x71>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x10>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+ cluster1_opp: opp-table-1 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-microvolt = <905000 905000 1140000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2150400000 {
+ opp-hz = /bits/ 64 <2150400000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x31>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2342400000 {
+ opp-hz = /bits/ 64 <2342400000>;
+ opp-microvolt = <1140000 905000 1140000>;
+ opp-supported-hw = <0x10>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qfprom: qfprom@74000 {
+ compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
+ reg = <0x00074000 0x8ff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ speedbin_efuse: speedbin@133 {
+ reg = <0x133 0x1>;
+ bits = <5 3>;
+ };
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml
new file mode 100644
index 000000000000..14a7a689ad6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm OPP bindings to describe OPP nodes.
+
+maintainers:
+ - Niklas Cassel <nks@flawful.org>
+
+allOf:
+ - $ref: opp-v2-base.yaml#
+
+properties:
+ compatible:
+ const: operating-points-v2-qcom-level
+
+patternProperties:
+ '^opp-?[0-9]+$':
+ type: object
+
+ properties:
+ opp-level: true
+
+ qcom,opp-fuse-level:
+ description: |
+ A positive value representing the fuse corner/level associated with
+ this OPP node. Sometimes several corners/levels shares a certain fuse
+ corner/level. A fuse corner/level contains e.g. ref uV, min uV,
+ and max uV.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ required:
+ - opp-level
+ - qcom,opp-fuse-level
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ cpr_opp_table: opp-table-cpr {
+ compatible = "operating-points-v2-qcom-level";
+
+ cpr_opp1: opp1 {
+ opp-level = <1>;
+ qcom,opp-fuse-level = <1>;
+ };
+ cpr_opp2: opp2 {
+ opp-level = <2>;
+ qcom,opp-fuse-level = <2>;
+ };
+ cpr_opp3: opp3 {
+ opp-level = <3>;
+ qcom,opp-fuse-level = <3>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
deleted file mode 100644
index 64f07417ecfb..000000000000
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ /dev/null
@@ -1,796 +0,0 @@
-Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
-===================================
-
-In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996,
-the CPU frequencies subset and voltage value of each OPP varies based on
-the silicon variant in use.
-Qualcomm Technologies, Inc. Process Voltage Scaling Tables
-defines the voltage and frequency value based on the msm-id in SMEM
-and speedbin blown in the efuse combination.
-The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
-to provide the OPP framework with required information (existing HW bitmap).
-This is used to determine the voltage and frequency value for each OPP of
-operating-points-v2 table when it is parsed by the OPP framework.
-
-Required properties:
---------------------
-In 'cpu' nodes:
-- operating-points-v2: Phandle to the operating-points-v2 table to use.
-
-In 'operating-points-v2' table:
-- compatible: Should be
- - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
- apq8064, ipq8064, msm8960 and ipq8074.
-
-Optional properties:
---------------------
-In 'cpu' nodes:
-- power-domains: A phandle pointing to the PM domain specifier which provides
- the performance states available for active state management.
- Please refer to the power-domains bindings
- Documentation/devicetree/bindings/power/power_domain.txt
- and also examples below.
-- power-domain-names: Should be
- - 'cpr' for qcs404.
-
-In 'operating-points-v2' table:
-- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
- efuse registers that has information about the
- speedbin that is used to select the right frequency/voltage
- value pair.
- Please refer the for nvmem-cells
- bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
- and also examples below.
-
-In every OPP node:
-- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
- Bitmap:
- 0: MSM8996 V3, speedbin 0
- 1: MSM8996 V3, speedbin 1
- 2: MSM8996 V3, speedbin 2
- 3: unused
- 4: MSM8996 SG, speedbin 0
- 5: MSM8996 SG, speedbin 1
- 6: MSM8996 SG, speedbin 2
- 7-31: unused
-
-Example 1:
----------
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- CPU0: cpu@0 {
- device_type = "cpu";
- compatible = "qcom,kryo";
- reg = <0x0 0x0>;
- enable-method = "psci";
- clocks = <&kryocc 0>;
- cpu-supply = <&pm8994_s11_saw>;
- operating-points-v2 = <&cluster0_opp>;
- #cooling-cells = <2>;
- next-level-cache = <&L2_0>;
- L2_0: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- };
- };
-
- CPU1: cpu@1 {
- device_type = "cpu";
- compatible = "qcom,kryo";
- reg = <0x0 0x1>;
- enable-method = "psci";
- clocks = <&kryocc 0>;
- cpu-supply = <&pm8994_s11_saw>;
- operating-points-v2 = <&cluster0_opp>;
- #cooling-cells = <2>;
- next-level-cache = <&L2_0>;
- };
-
- CPU2: cpu@100 {
- device_type = "cpu";
- compatible = "qcom,kryo";
- reg = <0x0 0x100>;
- enable-method = "psci";
- clocks = <&kryocc 1>;
- cpu-supply = <&pm8994_s11_saw>;
- operating-points-v2 = <&cluster1_opp>;
- #cooling-cells = <2>;
- next-level-cache = <&L2_1>;
- L2_1: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- };
- };
-
- CPU3: cpu@101 {
- device_type = "cpu";
- compatible = "qcom,kryo";
- reg = <0x0 0x101>;
- enable-method = "psci";
- clocks = <&kryocc 1>;
- cpu-supply = <&pm8994_s11_saw>;
- operating-points-v2 = <&cluster1_opp>;
- #cooling-cells = <2>;
- next-level-cache = <&L2_1>;
- };
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
-
- core1 {
- cpu = <&CPU1>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&CPU2>;
- };
-
- core1 {
- cpu = <&CPU3>;
- };
- };
- };
- };
-
- cluster0_opp: opp_table0 {
- compatible = "operating-points-v2-kryo-cpu";
- nvmem-cells = <&speedbin_efuse>;
- opp-shared;
-
- opp-307200000 {
- opp-hz = /bits/ 64 <307200000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x77>;
- clock-latency-ns = <200000>;
- };
- opp-384000000 {
- opp-hz = /bits/ 64 <384000000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-422400000 {
- opp-hz = /bits/ 64 <422400000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-460800000 {
- opp-hz = /bits/ 64 <460800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-480000000 {
- opp-hz = /bits/ 64 <480000000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-537600000 {
- opp-hz = /bits/ 64 <537600000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-556800000 {
- opp-hz = /bits/ 64 <556800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-614400000 {
- opp-hz = /bits/ 64 <614400000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-652800000 {
- opp-hz = /bits/ 64 <652800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-691200000 {
- opp-hz = /bits/ 64 <691200000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-729600000 {
- opp-hz = /bits/ 64 <729600000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-768000000 {
- opp-hz = /bits/ 64 <768000000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-844800000 {
- opp-hz = /bits/ 64 <844800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x77>;
- clock-latency-ns = <200000>;
- };
- opp-902400000 {
- opp-hz = /bits/ 64 <902400000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-960000000 {
- opp-hz = /bits/ 64 <960000000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-979200000 {
- opp-hz = /bits/ 64 <979200000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1036800000 {
- opp-hz = /bits/ 64 <1036800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1056000000 {
- opp-hz = /bits/ 64 <1056000000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1113600000 {
- opp-hz = /bits/ 64 <1113600000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1132800000 {
- opp-hz = /bits/ 64 <1132800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1190400000 {
- opp-hz = /bits/ 64 <1190400000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1209600000 {
- opp-hz = /bits/ 64 <1209600000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1228800000 {
- opp-hz = /bits/ 64 <1228800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1286400000 {
- opp-hz = /bits/ 64 <1286400000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1324800000 {
- opp-hz = /bits/ 64 <1324800000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x5>;
- clock-latency-ns = <200000>;
- };
- opp-1363200000 {
- opp-hz = /bits/ 64 <1363200000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x72>;
- clock-latency-ns = <200000>;
- };
- opp-1401600000 {
- opp-hz = /bits/ 64 <1401600000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x5>;
- clock-latency-ns = <200000>;
- };
- opp-1440000000 {
- opp-hz = /bits/ 64 <1440000000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1478400000 {
- opp-hz = /bits/ 64 <1478400000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x1>;
- clock-latency-ns = <200000>;
- };
- opp-1497600000 {
- opp-hz = /bits/ 64 <1497600000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x4>;
- clock-latency-ns = <200000>;
- };
- opp-1516800000 {
- opp-hz = /bits/ 64 <1516800000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1593600000 {
- opp-hz = /bits/ 64 <1593600000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x71>;
- clock-latency-ns = <200000>;
- };
- opp-1996800000 {
- opp-hz = /bits/ 64 <1996800000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x20>;
- clock-latency-ns = <200000>;
- };
- opp-2188800000 {
- opp-hz = /bits/ 64 <2188800000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x10>;
- clock-latency-ns = <200000>;
- };
- };
-
- cluster1_opp: opp_table1 {
- compatible = "operating-points-v2-kryo-cpu";
- nvmem-cells = <&speedbin_efuse>;
- opp-shared;
-
- opp-307200000 {
- opp-hz = /bits/ 64 <307200000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x77>;
- clock-latency-ns = <200000>;
- };
- opp-384000000 {
- opp-hz = /bits/ 64 <384000000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-403200000 {
- opp-hz = /bits/ 64 <403200000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-460800000 {
- opp-hz = /bits/ 64 <460800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-480000000 {
- opp-hz = /bits/ 64 <480000000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-537600000 {
- opp-hz = /bits/ 64 <537600000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-556800000 {
- opp-hz = /bits/ 64 <556800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-614400000 {
- opp-hz = /bits/ 64 <614400000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-652800000 {
- opp-hz = /bits/ 64 <652800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-691200000 {
- opp-hz = /bits/ 64 <691200000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-729600000 {
- opp-hz = /bits/ 64 <729600000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-748800000 {
- opp-hz = /bits/ 64 <748800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-806400000 {
- opp-hz = /bits/ 64 <806400000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-825600000 {
- opp-hz = /bits/ 64 <825600000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-883200000 {
- opp-hz = /bits/ 64 <883200000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-902400000 {
- opp-hz = /bits/ 64 <902400000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-940800000 {
- opp-hz = /bits/ 64 <940800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-979200000 {
- opp-hz = /bits/ 64 <979200000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1036800000 {
- opp-hz = /bits/ 64 <1036800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1056000000 {
- opp-hz = /bits/ 64 <1056000000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1113600000 {
- opp-hz = /bits/ 64 <1113600000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1132800000 {
- opp-hz = /bits/ 64 <1132800000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1190400000 {
- opp-hz = /bits/ 64 <1190400000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1209600000 {
- opp-hz = /bits/ 64 <1209600000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1248000000 {
- opp-hz = /bits/ 64 <1248000000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1286400000 {
- opp-hz = /bits/ 64 <1286400000>;
- opp-microvolt = <905000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1324800000 {
- opp-hz = /bits/ 64 <1324800000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1363200000 {
- opp-hz = /bits/ 64 <1363200000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1401600000 {
- opp-hz = /bits/ 64 <1401600000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1440000000 {
- opp-hz = /bits/ 64 <1440000000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1478400000 {
- opp-hz = /bits/ 64 <1478400000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1516800000 {
- opp-hz = /bits/ 64 <1516800000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1555200000 {
- opp-hz = /bits/ 64 <1555200000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1593600000 {
- opp-hz = /bits/ 64 <1593600000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1632000000 {
- opp-hz = /bits/ 64 <1632000000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1670400000 {
- opp-hz = /bits/ 64 <1670400000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1708800000 {
- opp-hz = /bits/ 64 <1708800000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1747200000 {
- opp-hz = /bits/ 64 <1747200000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x70>;
- clock-latency-ns = <200000>;
- };
- opp-1785600000 {
- opp-hz = /bits/ 64 <1785600000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x7>;
- clock-latency-ns = <200000>;
- };
- opp-1804800000 {
- opp-hz = /bits/ 64 <1804800000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x6>;
- clock-latency-ns = <200000>;
- };
- opp-1824000000 {
- opp-hz = /bits/ 64 <1824000000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x71>;
- clock-latency-ns = <200000>;
- };
- opp-1900800000 {
- opp-hz = /bits/ 64 <1900800000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x74>;
- clock-latency-ns = <200000>;
- };
- opp-1920000000 {
- opp-hz = /bits/ 64 <1920000000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x1>;
- clock-latency-ns = <200000>;
- };
- opp-1977600000 {
- opp-hz = /bits/ 64 <1977600000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x30>;
- clock-latency-ns = <200000>;
- };
- opp-1996800000 {
- opp-hz = /bits/ 64 <1996800000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x1>;
- clock-latency-ns = <200000>;
- };
- opp-2054400000 {
- opp-hz = /bits/ 64 <2054400000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x30>;
- clock-latency-ns = <200000>;
- };
- opp-2073600000 {
- opp-hz = /bits/ 64 <2073600000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x1>;
- clock-latency-ns = <200000>;
- };
- opp-2150400000 {
- opp-hz = /bits/ 64 <2150400000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x31>;
- clock-latency-ns = <200000>;
- };
- opp-2246400000 {
- opp-hz = /bits/ 64 <2246400000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x10>;
- clock-latency-ns = <200000>;
- };
- opp-2342400000 {
- opp-hz = /bits/ 64 <2342400000>;
- opp-microvolt = <1140000 905000 1140000>;
- opp-supported-hw = <0x10>;
- clock-latency-ns = <200000>;
- };
- };
-
-....
-
-reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-....
- smem_mem: smem-mem@86000000 {
- reg = <0x0 0x86000000 0x0 0x200000>;
- no-map;
- };
-....
-};
-
-smem {
- compatible = "qcom,smem";
- memory-region = <&smem_mem>;
- hwlocks = <&tcsr_mutex 3>;
-};
-
-soc {
-....
- qfprom: qfprom@74000 {
- compatible = "qcom,qfprom";
- reg = <0x00074000 0x8ff>;
- #address-cells = <1>;
- #size-cells = <1>;
- ....
- speedbin_efuse: speedbin@133 {
- reg = <0x133 0x1>;
- bits = <5 3>;
- };
- };
-};
-
-Example 2:
----------
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- CPU0: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x100>;
- ....
- clocks = <&apcs_glb>;
- operating-points-v2 = <&cpu_opp_table>;
- power-domains = <&cpr>;
- power-domain-names = "cpr";
- };
-
- CPU1: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x101>;
- ....
- clocks = <&apcs_glb>;
- operating-points-v2 = <&cpu_opp_table>;
- power-domains = <&cpr>;
- power-domain-names = "cpr";
- };
-
- CPU2: cpu@102 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x102>;
- ....
- clocks = <&apcs_glb>;
- operating-points-v2 = <&cpu_opp_table>;
- power-domains = <&cpr>;
- power-domain-names = "cpr";
- };
-
- CPU3: cpu@103 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x103>;
- ....
- clocks = <&apcs_glb>;
- operating-points-v2 = <&cpu_opp_table>;
- power-domains = <&cpr>;
- power-domain-names = "cpr";
- };
- };
-
- cpu_opp_table: cpu-opp-table {
- compatible = "operating-points-v2-kryo-cpu";
- opp-shared;
-
- opp-1094400000 {
- opp-hz = /bits/ 64 <1094400000>;
- required-opps = <&cpr_opp1>;
- };
- opp-1248000000 {
- opp-hz = /bits/ 64 <1248000000>;
- required-opps = <&cpr_opp2>;
- };
- opp-1401600000 {
- opp-hz = /bits/ 64 <1401600000>;
- required-opps = <&cpr_opp3>;
- };
- };
-
- cpr_opp_table: cpr-opp-table {
- compatible = "operating-points-v2-qcom-level";
-
- cpr_opp1: opp1 {
- opp-level = <1>;
- qcom,opp-fuse-level = <1>;
- };
- cpr_opp2: opp2 {
- opp-level = <2>;
- qcom,opp-fuse-level = <2>;
- };
- cpr_opp3: opp3 {
- opp-level = <3>;
- qcom,opp-fuse-level = <3>;
- };
- };
-
-....
-
-soc {
-....
- cpr: power-controller@b018000 {
- compatible = "qcom,qcs404-cpr", "qcom,cpr";
- reg = <0x0b018000 0x1000>;
- ....
- vdd-apc-supply = <&pms405_s3>;
- #power-domain-cells = <0>;
- operating-points-v2 = <&cpr_opp_table>;
- ....
- };
-};
diff --git a/Documentation/devicetree/bindings/opp/qcom-opp.txt b/Documentation/devicetree/bindings/opp/qcom-opp.txt
deleted file mode 100644
index 41d3e4ff2dc3..000000000000
--- a/Documentation/devicetree/bindings/opp/qcom-opp.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Qualcomm OPP bindings to describe OPP nodes
-
-The bindings are based on top of the operating-points-v2 bindings
-described in Documentation/devicetree/bindings/opp/opp-v2-base.yaml
-Additional properties are described below.
-
-* OPP Table Node
-
-Required properties:
-- compatible: Allow OPPs to express their compatibility. It should be:
- "operating-points-v2-qcom-level"
-
-* OPP Node
-
-Required properties:
-- qcom,opp-fuse-level: A positive value representing the fuse corner/level
- associated with this OPP node. Sometimes several corners/levels shares
- a certain fuse corner/level. A fuse corner/level contains e.g. ref uV,
- min uV, and max uV.
diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
deleted file mode 100644
index ab0d5ebbad4e..000000000000
--- a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
+++ /dev/null
@@ -1,130 +0,0 @@
-QCOM CPR (Core Power Reduction)
-
-CPR (Core Power Reduction) is a technology to reduce core power on a CPU
-or other device. Each OPP of a device corresponds to a "corner" that has
-a range of valid voltages for a particular frequency. While the device is
-running at a particular frequency, CPR monitors dynamic factors such as
-temperature, etc. and suggests adjustments to the voltage to save power
-and meet silicon characteristic requirements.
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: base address and size of the rbcpr register region
-
-- interrupts:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: should specify the CPR interrupt
-
-- clocks:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: phandle to the reference clock
-
-- clock-names:
- Usage: required
- Value type: <stringlist>
- Definition: must be "ref"
-
-- vdd-apc-supply:
- Usage: required
- Value type: <phandle>
- Definition: phandle to the vdd-apc-supply regulator
-
-- #power-domain-cells:
- Usage: required
- Value type: <u32>
- Definition: should be 0
-
-- operating-points-v2:
- Usage: required
- Value type: <phandle>
- Definition: A phandle to the OPP table containing the
- performance states supported by the CPR
- power domain
-
-- acc-syscon:
- Usage: optional
- Value type: <phandle>
- Definition: phandle to syscon for writing ACC settings
-
-- nvmem-cells:
- Usage: required
- Value type: <phandle>
- Definition: phandle to nvmem cells containing the data
- that makes up a fuse corner, for each fuse corner.
- As well as the CPR fuse revision.
-
-- nvmem-cell-names:
- Usage: required
- Value type: <stringlist>
- Definition: should be "cpr_quotient_offset1", "cpr_quotient_offset2",
- "cpr_quotient_offset3", "cpr_init_voltage1",
- "cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1",
- "cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1",
- "cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision"
- for qcs404.
-
-Example:
-
- cpr_opp_table: cpr-opp-table {
- compatible = "operating-points-v2-qcom-level";
-
- cpr_opp1: opp1 {
- opp-level = <1>;
- qcom,opp-fuse-level = <1>;
- };
- cpr_opp2: opp2 {
- opp-level = <2>;
- qcom,opp-fuse-level = <2>;
- };
- cpr_opp3: opp3 {
- opp-level = <3>;
- qcom,opp-fuse-level = <3>;
- };
- };
-
- power-controller@b018000 {
- compatible = "qcom,qcs404-cpr", "qcom,cpr";
- reg = <0x0b018000 0x1000>;
- interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xo_board>;
- clock-names = "ref";
- vdd-apc-supply = <&pms405_s3>;
- #power-domain-cells = <0>;
- operating-points-v2 = <&cpr_opp_table>;
- acc-syscon = <&tcsr>;
-
- nvmem-cells = <&cpr_efuse_quot_offset1>,
- <&cpr_efuse_quot_offset2>,
- <&cpr_efuse_quot_offset3>,
- <&cpr_efuse_init_voltage1>,
- <&cpr_efuse_init_voltage2>,
- <&cpr_efuse_init_voltage3>,
- <&cpr_efuse_quot1>,
- <&cpr_efuse_quot2>,
- <&cpr_efuse_quot3>,
- <&cpr_efuse_ring1>,
- <&cpr_efuse_ring2>,
- <&cpr_efuse_ring3>,
- <&cpr_efuse_revision>;
- nvmem-cell-names = "cpr_quotient_offset1",
- "cpr_quotient_offset2",
- "cpr_quotient_offset3",
- "cpr_init_voltage1",
- "cpr_init_voltage2",
- "cpr_init_voltage3",
- "cpr_quotient1",
- "cpr_quotient2",
- "cpr_quotient3",
- "cpr_ring_osc1",
- "cpr_ring_osc2",
- "cpr_ring_osc3",
- "cpr_fuse_revision";
- };
diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml b/Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
new file mode 100644
index 000000000000..3301fa0c2653
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/avs/qcom,cpr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Core Power Reduction (CPR) bindings
+
+maintainers:
+ - Niklas Cassel <nks@flawful.org>
+
+description: |
+ CPR (Core Power Reduction) is a technology to reduce core power on a CPU
+ or other device. Each OPP of a device corresponds to a "corner" that has
+ a range of valid voltages for a particular frequency. While the device is
+ running at a particular frequency, CPR monitors dynamic factors such as
+ temperature, etc. and suggests adjustments to the voltage to save power
+ and meet silicon characteristic requirements.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,qcs404-cpr
+ - const: qcom,cpr
+
+ reg:
+ description: Base address and size of the RBCPR register region.
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Reference clock.
+
+ clock-names:
+ items:
+ - const: ref
+
+ vdd-apc-supply:
+ description: APC regulator supply.
+
+ '#power-domain-cells':
+ const: 0
+
+ operating-points-v2:
+ description: |
+ A phandle to the OPP table containing the performance states
+ supported by the CPR power domain.
+
+ acc-syscon:
+ description: A phandle to the syscon used for writing ACC settings.
+
+ nvmem-cells:
+ items:
+ - description: Corner 1 quotient offset
+ - description: Corner 2 quotient offset
+ - description: Corner 3 quotient offset
+ - description: Corner 1 initial voltage
+ - description: Corner 2 initial voltage
+ - description: Corner 3 initial voltage
+ - description: Corner 1 quotient
+ - description: Corner 2 quotient
+ - description: Corner 3 quotient
+ - description: Corner 1 ring oscillator
+ - description: Corner 2 ring oscillator
+ - description: Corner 3 ring oscillator
+ - description: Fuse revision
+
+ nvmem-cell-names:
+ items:
+ - const: cpr_quotient_offset1
+ - const: cpr_quotient_offset2
+ - const: cpr_quotient_offset3
+ - const: cpr_init_voltage1
+ - const: cpr_init_voltage2
+ - const: cpr_init_voltage3
+ - const: cpr_quotient1
+ - const: cpr_quotient2
+ - const: cpr_quotient3
+ - const: cpr_ring_osc1
+ - const: cpr_ring_osc2
+ - const: cpr_ring_osc3
+ - const: cpr_fuse_revision
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - vdd-apc-supply
+ - '#power-domain-cells'
+ - operating-points-v2
+ - nvmem-cells
+ - nvmem-cell-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ cpr_opp_table: opp-table-cpr {
+ compatible = "operating-points-v2-qcom-level";
+
+ cpr_opp1: opp1 {
+ opp-level = <1>;
+ qcom,opp-fuse-level = <1>;
+ };
+ cpr_opp2: opp2 {
+ opp-level = <2>;
+ qcom,opp-fuse-level = <2>;
+ };
+ cpr_opp3: opp3 {
+ opp-level = <3>;
+ qcom,opp-fuse-level = <3>;
+ };
+ };
+
+ power-controller@b018000 {
+ compatible = "qcom,qcs404-cpr", "qcom,cpr";
+ reg = <0x0b018000 0x1000>;
+ interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xo_board>;
+ clock-names = "ref";
+ vdd-apc-supply = <&pms405_s3>;
+ #power-domain-cells = <0>;
+ operating-points-v2 = <&cpr_opp_table>;
+ acc-syscon = <&tcsr>;
+
+ nvmem-cells = <&cpr_efuse_quot_offset1>,
+ <&cpr_efuse_quot_offset2>,
+ <&cpr_efuse_quot_offset3>,
+ <&cpr_efuse_init_voltage1>,
+ <&cpr_efuse_init_voltage2>,
+ <&cpr_efuse_init_voltage3>,
+ <&cpr_efuse_quot1>,
+ <&cpr_efuse_quot2>,
+ <&cpr_efuse_quot3>,
+ <&cpr_efuse_ring1>,
+ <&cpr_efuse_ring2>,
+ <&cpr_efuse_ring3>,
+ <&cpr_efuse_revision>;
+ nvmem-cell-names = "cpr_quotient_offset1",
+ "cpr_quotient_offset2",
+ "cpr_quotient_offset3",
+ "cpr_init_voltage1",
+ "cpr_init_voltage2",
+ "cpr_init_voltage3",
+ "cpr_quotient1",
+ "cpr_quotient2",
+ "cpr_quotient3",
+ "cpr_ring_osc1",
+ "cpr_ring_osc2",
+ "cpr_ring_osc3",
+ "cpr_fuse_revision";
+ };