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authorGeert Uytterhoeven <geert+renesas@glider.be>2020-09-09 16:15:34 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2020-09-15 11:04:35 +0300
commit540d9757cea8274a44d69cbadcff5b8c381bae8d (patch)
tree670add1f0573caa1b83cf5a0bb3f16e48db39ec4 /Documentation/devicetree
parent077365a941166f3a7f5894017f9d26d17cdec00e (diff)
downloadlinux-540d9757cea8274a44d69cbadcff5b8c381bae8d.tar.xz
pinctrl: renesas: Reintroduce SH_PFC for common sh-pfc code
Most, but not all, Renesas pin control drivers use the "sh-pfc" pin control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc: Collect Renesas related CONFIGs in one place"), the code for this framework is always built when Renesas SoC pin control support is enabled, regardless of whether the enabled pin control drivers need it or not. Fix this by reintroducing the CONFIG_SH_PFC symbol to control inclusion of the "sh-pfc" framework and its dependencies, and selecting it when needed. This reduces kernel size of a typical RZ/A1 or RZ/A2 kernel by more than 6 resp. 11 KiB. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-4-geert+renesas@glider.be
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