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authorAndrew Jeffery <andrew@aj.id.au>2019-10-10 05:07:25 +0300
committerStephen Boyd <sboyd@kernel.org>2019-11-08 19:48:41 +0300
commit3696eebd810cf084b3662d3c3b85cd84b61090f3 (patch)
treec948172d8bd4687a297837c14d97c04edbd13759 /Documentation/devicetree
parent309d673e9596f9706e72615583f2f689cf3fbfb5 (diff)
downloadlinux-3696eebd810cf084b3662d3c3b85cd84b61090f3.tar.xz
clk: ast2600: Add RMII RCLK gates for all four MACs
RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a single gate for each MAC. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lkml.kernel.org/r/20191010020725.3990-3-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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