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| author | Olof Johansson <olof@lixom.net> | 2012-11-30 21:08:56 +0400 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2012-11-30 21:08:56 +0400 |
| commit | 5e5d8999a316d596f2012fe1cf4c59e0de693dab (patch) | |
| tree | 56d0aeed586f34e97acbc78759606fddb3ba0627 /Documentation/devicetree/bindings | |
| parent | 0c0029cb1806601430692d48c130a17302a18225 (diff) | |
| parent | 3ee11aef75db51c69cb8cb91dd01afb28036f1b5 (diff) | |
| download | linux-5e5d8999a316d596f2012fe1cf4c59e0de693dab.tar.xz | |
Merge tag 'mvebu_cache_l2x0_for_3.8' of git://git.infradead.org/users/jcooper/linux into late/mvebu
From Jason Cooper:
mvebu cache-l2x0 for v3.8
- Add support for l2x0 cache on mvebu boards
- Depends on mvebu/everything
* tag 'mvebu_cache_l2x0_for_3.8' of git://git.infradead.org/users/jcooper/linux:
arm: l2x0: add aurora related properties to OF binding
arm: mvebu: add Aurora L2 Cache Controller to the DT
arm: mvebu: add L2 cache support
Diffstat (limited to 'Documentation/devicetree/bindings')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/l2cc.txt | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index 7ca52161e7ab..76b0ee6ee9a4 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -10,6 +10,12 @@ Required properties: "arm,pl310-cache" "arm,l220-cache" "arm,l210-cache" + "marvell,aurora-system-cache": Marvell Controller designed to be + compatible with the ARM one, with system cache mode (meaning + maintenance operations on L1 are broadcasted to the L2 and L2 + performs the same operation). + "marvell,"aurora-outer-cache: Marvell Controller designed to be + compatible with the ARM one with outer cache mode. - cache-unified : Specifies the cache is a unified cache. - cache-level : Should be set to 2 for a level 2 cache. - reg : Physical base address and size of cache controller's memory mapped @@ -29,6 +35,9 @@ Optional properties: filter. Addresses in the filter window are directed to the M1 port. Other addresses will go to the M0 port. - interrupts : 1 combined interrupt. +- cache-id-part: cache id part number to be used if it is not present + on hardware +- wt-override: If present then L2 is forced to Write through mode Example: |