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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-16 01:03:48 +0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-16 01:03:48 +0400
commit2b8318881ddbcb67c5e8d2178b42284749442222 (patch)
treeb43ded0118bb7a6d9f89f6875c18d7ef447ba3be /Documentation/devicetree/bindings/video/exynos_dp.txt
parente81d372ff9f694e13fa46e8b5aaed505c7fd2a1f (diff)
parente7f5c9a16ea2648a3e85af8e34191026bf3dcb62 (diff)
downloadlinux-2b8318881ddbcb67c5e8d2178b42284749442222.tar.xz
Merge tag 'fbdev-for-3.8' of git://gitorious.org/linux-omap-dss2/linux
Pull fbdev changes from Tomi Valkeinen: "OMAPDSS changes, including: - use dynanic debug prints - OMAP platform dependency removals - Creation of compat-layer, helping us to improve omapdrm - Misc cleanups, aiming to make omadss more in line with the upcoming common display framework Exynos DP changes for the 3.8 merge window: - Device Tree support for Samsung Exynos DP - SW Link training is cleaned up. - HPD interrupt is supported. Samsung Framebuffer changes for the 3.8 merge window: - The bit definitions of header file are updated. - Some minor typos are fixed. - Some minor bugs of s3c_fb_check_var() are fixed. FB related changes for SH Mobile, Freescale DIU Add support for the Solomon SSD1307 OLED Controller" * tag 'fbdev-for-3.8' of git://gitorious.org/linux-omap-dss2/linux: (191 commits) OMAPDSS: fix TV-out issue with DSI PLL Revert "OMAPFB: simplify locking" OMAPFB: remove silly loop in fb2display() OMAPFB: fix error handling in omapfb_find_best_mode() OMAPFB: use devm_kzalloc to allocate omapfb2_device OMAPDSS: DISPC: remove dispc fck uses OMAPDSS: DISPC: get dss clock rate from dss driver drivers/video/console/softcursor.c: remove redundant NULL check before kfree() drivers/video: add support for the Solomon SSD1307 OLED Controller OMAPDSS: use omapdss_compat_init() in other drivers OMAPDSS: export dispc functions OMAPDSS: export dss_feat functions OMAPDSS: export dss_mgr_ops functions OMAPDSS: separate compat files in the Makefile OMAPDSS: move display sysfs init to compat layer OMAPDSS: DPI: use dispc's check_timings OMAPDSS: DISPC: add dispc_ovl_check() OMAPDSS: move irq handling to dispc-compat OMAPDSS: move omap_dispc_wait_for_irq_interruptible_timeout to dispc-compat.c OMAPDSS: move blocking mgr enable/disable to compat layer ... Conflicts: arch/arm/mach-davinci/devices-da8xx.c arch/arm/plat-omap/common.c drivers/media/platform/omap/omap_vout.c
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+The Exynos display port interface should be configured based on
+the type of panel connected to it.
+
+We use two nodes:
+ -dp-controller node
+ -dptx-phy node(defined inside dp-controller node)
+
+For the DP-PHY initialization, we use the dptx-phy node.
+Required properties for dptx-phy:
+ -reg:
+ Base address of DP PHY register.
+ -samsung,enable-mask:
+ The bit-mask used to enable/disable DP PHY.
+
+For the Panel initialization, we read data from dp-controller node.
+Required properties for dp-controller:
+ -compatible:
+ should be "samsung,exynos5-dp".
+ -reg:
+ physical base address of the controller and length
+ of memory mapped region.
+ -interrupts:
+ interrupt combiner values.
+ -interrupt-parent:
+ phandle to Interrupt combiner node.
+ -samsung,color-space:
+ input video data format.
+ COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
+ -samsung,dynamic-range:
+ dynamic range for input video data.
+ VESA = 0, CEA = 1
+ -samsung,ycbcr-coeff:
+ YCbCr co-efficients for input video.
+ COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
+ -samsung,color-depth:
+ number of bits per colour component.
+ COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
+ -samsung,link-rate:
+ link rate supported by the panel.
+ LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
+ -samsung,lane-count:
+ number of lanes supported by the panel.
+ LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
+
+Optional properties for dp-controller:
+ -interlaced:
+ interlace scan mode.
+ Progressive if defined, Interlaced if not defined
+ -vsync-active-high:
+ VSYNC polarity configuration.
+ High if defined, Low if not defined
+ -hsync-active-high:
+ HSYNC polarity configuration.
+ High if defined, Low if not defined
+
+Example:
+
+SOC specific portion:
+ dp-controller {
+ compatible = "samsung,exynos5-dp";
+ reg = <0x145b0000 0x10000>;
+ interrupts = <10 3>;
+ interrupt-parent = <&combiner>;
+
+ dptx-phy {
+ reg = <0x10040720>;
+ samsung,enable-mask = <1>;
+ };
+
+ };
+
+Board Specific portion:
+ dp-controller {
+ samsung,color-space = <0>;
+ samsung,dynamic-range = <0>;
+ samsung,ycbcr-coeff = <0>;
+ samsung,color-depth = <1>;
+ samsung,link-rate = <0x0a>;
+ samsung,lane-count = <4>;
+ };