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| author | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2018-07-31 17:38:53 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2018-07-31 17:41:14 +0300 |
| commit | f09757ab401ff332030f8e3a41cec6a44e6d9461 (patch) | |
| tree | 4795cd87d9a1585d105fc641b80ed1e1d507e39e /Documentation/devicetree/bindings/spi | |
| parent | baec8eb323cd59d1bfe148a287610819d5897838 (diff) | |
| download | linux-f09757ab401ff332030f8e3a41cec6a44e6d9461.tar.xz | |
spi: dw: document Microsemi integration
The integration of the Designware SPI controller on Microsemi SoCs requires
an extra register set to be able to give the IP control of the SPI
interface.
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
| -rw-r--r-- | Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 204b311e0400..642d3fb1ef85 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -1,8 +1,10 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. Required properties: -- compatible : "snps,dw-apb-ssi" -- reg : The register base for the controller. +- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or + "jaguar2" +- reg : The register base for the controller. For "mscc,<soc>-spi", a second + register set is required (named ICPU_CFG:SPI_MST) - interrupts : One interrupt, used by the controller. - #address-cells : <1>, as required by generic SPI binding. - #size-cells : <0>, also as required by generic SPI binding. |