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authorChuanhong Guo <gch981213@gmail.com>2022-04-24 06:25:26 +0300
committerMark Brown <broonie@kernel.org>2022-04-27 19:22:54 +0300
commit69bb9b29bf67e850beece45e9c99ca707eac7e41 (patch)
tree2f22e7067c8e75117e76d54f07a0ccd799e085fb /Documentation/devicetree/bindings/spi
parent764f1b7481645b2b4488eda26c4da7f331697e6b (diff)
downloadlinux-69bb9b29bf67e850beece45e9c99ca707eac7e41.tar.xz
spi: dt-bindings: add binding doc for spi-mtk-snfi
Add device-tree binding documentation for Mediatek SPI-NAND Flash Interface. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220424032527.673605-5-gch981213@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
-rw-r--r--Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml88
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diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml
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+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SPI-NAND flash controller for MediaTek ARM SoCs
+
+maintainers:
+ - Chuanhong Guo <gch981213@gmail.com>
+
+description: |
+ The Mediatek SPI-NAND flash controller is an extended version of
+ the Mediatek NAND flash controller. It can perform standard SPI
+ instructions with one continuous write and one read for up-to 0xa0
+ bytes. It also supports typical SPI-NAND page cache operations
+ in single, dual or quad IO mode with pipelined ECC encoding/decoding
+ using the accompanying ECC engine. There should be only one spi
+ slave device following generic spi bindings.
+
+allOf:
+ - $ref: /schemas/spi/spi-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt7622-snand
+ - mediatek,mt7629-snand
+
+ reg:
+ items:
+ - description: core registers
+
+ interrupts:
+ items:
+ - description: NFI interrupt
+
+ clocks:
+ items:
+ - description: clock used for the controller
+ - description: clock used for the SPI bus
+
+ clock-names:
+ items:
+ - const: nfi_clk
+ - const: pad_clk
+
+ nand-ecc-engine:
+ description: device-tree node of the accompanying ECC engine.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - nand-ecc-engine
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt7622-clk.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ snfi: spi@1100d000 {
+ compatible = "mediatek,mt7622-snand";
+ reg = <0 0x1100d000 0 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "pad_clk";
+ nand-ecc-engine = <&bch>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ nand-ecc-engine = <&snfi>;
+ };
+ };
+ };