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| author | Andreas Larsson <andreas@gaisler.com> | 2013-02-15 19:52:26 +0400 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2013-04-07 13:07:56 +0400 |
| commit | 447b0c7b939f1d9e4024edf07a471ce7b1bcf002 (patch) | |
| tree | ba1118bd6bbf30af8fe4622f8c7d9ad103c9f566 /Documentation/devicetree/bindings/spi | |
| parent | 8922a366ddd20964e3542e12f0315a8a88b3a638 (diff) | |
| download | linux-447b0c7b939f1d9e4024edf07a471ce7b1bcf002.tar.xz | |
spi/spi-fsl-spi: Add support for Aeroflex Gaisler GRLIB cores normally running on SPARC
This adds support for the mostly register-compatible SPICTRL cores from the
GRLIB VHDL IP core library from Aeroflex Gaisler. They are normally running on
SPARC. A different entry in of_fsl_spi_match matches this core and indicates a
different hardware type that is used to set up different function pointers and
special cases.
The GRLIB core operates in cpu mode. The number of bits per word might be
limited. There might be native chipselects selected via a slave select
register. These differences to the FSL type cores, if present, are indicated by
a capabilities register. Other register and function differences exists but are
not relevant to the driver.
Acked-by: Anton Vorontsov <anton@enomsg.org>
Signed-off-by: Andreas Larsson <andreas@gaisler.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
| -rw-r--r-- | Documentation/devicetree/bindings/spi/fsl-spi.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/spi/fsl-spi.txt b/Documentation/devicetree/bindings/spi/fsl-spi.txt index 4f2ea9461797..b032dd76e9d2 100644 --- a/Documentation/devicetree/bindings/spi/fsl-spi.txt +++ b/Documentation/devicetree/bindings/spi/fsl-spi.txt @@ -4,7 +4,7 @@ Required properties: - cell-index : QE SPI subblock index. 0: QE subblock SPI1 1: QE subblock SPI2 -- compatible : should be "fsl,spi". +- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl". - mode : the SPI operation mode, it can be "cpu" or "cpu-qe". - reg : Offset and length of the register set for the device - interrupts : <a b> where a is the interrupt number and b is a |