Merge tag 'spi-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi Updates from Mark Brown:
 "A busy release for both cleanups and new drivers this time along with
  further factoring out of replicated code into the core:

   - Provide support in the core for DMA mapping transfers - essentially
     all drivers weren't implementing this properly, now there's no
     excuse.
   - Dual and quad mode support for spidev.
   - Fix handling of cs_change in the generic implementation.
   - Remove the S3C_DMA code from the s3c64xx driver now that all the
     platforms using it have been converted to dmaengine.
   - Lots of improvements to the Renesas SPI controllers.
   - Drivers for Allwinner A10 and A31, Qualcomm QUP and Xylinx xtfpga.
   - Removal of the bitrotted ti-ssp driver"

* tag 'spi-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (199 commits)
  spi: Fix handling of cs_change in core implementation
  spi: bitbang: Make spi_bitbang_stop() return void
  spi: mpc52xx: Convert to use bits_per_word_mask
  spi: omap-100k: Fix memory leak
  spi: dw: Don't call kfree for memory allocated by devm_kzalloc
  spi: fsl-dspi: Fix memory leak
  spi: omap-uwire: add missing iounmap
  spi: clps711x: Convert to use master->max_speed_hz
  spi: clps711x: Enable driver compilation with COMPILE_TEST
  spi: omap-uwire: Remove full duplex check
  spi: Do not require a completion
  spi: topcliff-pch: Transform noisy message to dev_vdbg
  spi: coldfire-qspi: Simplify the code to set register bits for transfer speed
  spi: bcm63xx: Remove unused define for PFX
  spi: efm32: use $vendor,$device scheme for compatible string
  spi: clps711x: Remove <mach/hardware.h> dependency
  spi: topcliff-pch: Properly unregister platform devices on probe() error paths
  spi: fsl-espi: Remove unused bits_per_word variable in fsl_espi_bufs
  spi: altera: Remove the code to get unused platform_data
  spi: fsl-lib: Fix memory leak of pinfo
  ...

1 files changed, 85 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
new file mode 100644
index 000000000000..b82a268f1bd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
@@ -0,0 +1,85 @@
+Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
+
+The QUP core is an AHB slave that provides a common data path (an output FIFO
+and an input FIFO) for serial peripheral interface (SPI) mini-core.
+
+SPI in master mode supports up to 50MHz, up to four chip selects, programmable
+data path from 4 bits to 32 bits and numerous protocol variants.
+
+Required properties:
+- compatible:     Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
+- reg:            Should contain base register location and length
+- interrupts:     Interrupt number used by this controller
+
+- clocks:         Should contain the core clock and the AHB clock.
+- clock-names:    Should be "core" for the core clock and "iface" for the
+                  AHB clock.
+
+- #address-cells: Number of cells required to define a chip select
+                  address on the SPI bus. Should be set to 1.
+- #size-cells:    Should be zero.
+
+Optional properties:
+- spi-max-frequency: Specifies maximum SPI clock frequency,
+                     Units - Hz. Definition as per
+                     Documentation/devicetree/bindings/spi/spi-bus.txt
+
+SPI slave nodes must be children of the SPI master node and can contain
+properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+	spi_8: spi@f9964000 { /* BLSP2 QUP2 */
+
+		compatible = "qcom,spi-qup-v2";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0xf9964000 0x1000>;
+		interrupts = <0 102 0>;
+		spi-max-frequency = <19200000>;
+
+		clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+		clock-names = "core", "iface";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi8_default>;
+
+		device@0 {
+			compatible = "arm,pl022-dummy";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0>; /* Chip select 0 */
+			spi-max-frequency = <19200000>;
+			spi-cpol;
+		};
+
+		device@1 {
+			compatible = "arm,pl022-dummy";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <1>; /* Chip select 1 */
+			spi-max-frequency = <9600000>;
+			spi-cpha;
+		};
+
+		device@2 {
+			compatible = "arm,pl022-dummy";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <2>; /* Chip select 2 */
+			spi-max-frequency = <19200000>;
+			spi-cpol;
+			spi-cpha;
+		};
+
+		device@3 {
+			compatible = "arm,pl022-dummy";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <3>; /* Chip select 3 */
+			spi-max-frequency = <19200000>;
+			spi-cpol;
+			spi-cpha;
+			spi-cs-high;
+		};
+	};