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| author | Lucas Stach <l.stach@pengutronix.de> | 2022-12-16 23:08:17 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2023-01-01 06:00:30 +0300 |
| commit | ba70e1733238b3d4b53a5f030db629d3331110ec (patch) | |
| tree | 53b706c5bfe49942b3d87d68437898f23b106414 /Documentation/devicetree/bindings/soc/imx | |
| parent | 2da3647e2363d4eaaf9bd57da5c3bdc7b6d44f4a (diff) | |
| download | linux-ba70e1733238b3d4b53a5f030db629d3331110ec.tar.xz | |
dt-bindings: soc: imx8mp-hsio-blk-ctrl: add clock cells
The HSIO blk-ctrl has a internal PLL, which can be used as a reference
clock for the PCIe PHY. Add clock-cells to the binding to allow the
driver to expose this PLL.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/soc/imx')
| -rw-r--r-- | Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml index c29181a9745b..1fe68b53b1d8 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml @@ -39,6 +39,9 @@ properties: - const: pcie - const: pcie-phy + '#clock-cells': + const: 0 + clocks: minItems: 2 maxItems: 2 @@ -85,4 +88,5 @@ examples: power-domain-names = "bus", "usb", "usb-phy1", "usb-phy2", "pcie", "pcie-phy"; #power-domain-cells = <1>; + #clock-cells = <0>; }; |