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| author | Samuel Holland <samuel@sholland.org> | 2022-08-15 08:08:05 +0300 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2022-11-20 14:10:48 +0300 |
| commit | 41adc2fbad8bc42ed5fdf480e5318133a4941bbb (patch) | |
| tree | 05e8e54b6b04c73bb7aebed4fd37ed3b9c8c959e /Documentation/devicetree/bindings/riscv | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff) | |
| download | linux-41adc2fbad8bc42ed5fdf480e5318133a4941bbb.tar.xz | |
dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C906 core is used in the Allwinner D1 SoC.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 90a7cabf58fe..e98a716c6f18 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -39,6 +39,8 @@ properties: - sifive,u5 - sifive,u7 - canaan,k210 + - thead,c906 + - thead,c910 - const: riscv - items: - enum: |