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| author | Emil Renner Berthing <kernel@esmil.dk> | 2022-12-20 04:12:44 +0300 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2022-12-27 01:50:15 +0300 |
| commit | 1caf002efa223f930ba508159535cf82ad4b2811 (patch) | |
| tree | a84ab0659337c0d740e9a724d2f9ba647e5dfda2 /Documentation/devicetree/bindings/riscv | |
| parent | 1b929c02afd37871d5afb9d498426f83432e71c2 (diff) | |
| download | linux-1caf002efa223f930ba508159535cf82ad4b2811.tar.xz | |
dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
This cache controller is also used on the StarFive JH7110 SoC.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index bf3f07421f7e..31d20efaa6d3 100644 --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -39,6 +39,10 @@ properties: - sifive,fu740-c000-ccache - const: cache - items: + - const: starfive,jh7110-ccache + - const: sifive,ccache0 + - const: cache + - items: - const: microchip,mpfs-ccache - const: sifive,fu540-c000-ccache - const: cache @@ -85,6 +89,7 @@ allOf: contains: enum: - sifive,fu740-c000-ccache + - starfive,jh7110-ccache - microchip,mpfs-ccache then: @@ -105,7 +110,9 @@ allOf: properties: compatible: contains: - const: sifive,fu740-c000-ccache + enum: + - sifive,fu740-c000-ccache + - starfive,jh7110-ccache then: properties: |