Merge tag 'devicetree-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:

 - Update dtc to upstream version v1.6.0-31-gcbca977ea121

 - dtx_diff help text reformatting

 - Speed-up validation time for binding and dtb checks using json for
   intermediate files

 - Add support for running yamllint on DT schema files

 - Remove old booting-without-of.rst

 - Extend the example schema to address common issues

 - Cleanup handling of additionalProperties/unevaluatedProperties

 - Ensure all DSI controller schemas reference dsi-controller.yaml

 - Vendor prefixes for Zealz, Wandbord/Technexion, Embest RIoT, Rex,
   DFI, and Cisco Meraki

 - Convert at25, SPMI bus, TI hwlock, HiSilicon Hi3660 USB3 PHY, Arm
   SP805 watchdog, Arm SP804, and Samsung 11-pin USB connector to DT
   schema

 - Convert HiSilicon SoC and syscon bindings to DT schema

 - Convert SiFive Risc-V L2 cache, PLIC, PRCI, and PWM to DT schema

 - Convert i.MX bindings for w1, crypto, rng, SIM, PM, DDR, SATA, vf610
   GPIO, and UART to DT schema

 - Add i.MX 8M compatible strings

 - Add LM81 and DS1780 as trivial devices

 - Various missing properties added to fix dtb validation warnings

* tag 'devicetree-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (111 commits)
  dt-bindings: misc: explicitly add #address-cells for slave mode
  spi: dt-bindings: spi-controller: explicitly require #address-cells=<0> for slave mode
  dt: Remove booting-without-of.rst
  dt-bindings: update usb-c-connector example
  dt-bindings: arm: hisilicon: add missing properties into cpuctrl.yaml
  dt-bindings: arm: hisilicon: add missing properties into sysctrl.yaml
  dt-bindings: pwm: imx: document i.MX compatibles
  scripts/dtc: Update to upstream version v1.6.0-31-gcbca977ea121
  dt-bindings: Add running yamllint to dt_binding_check
  dt-bindings: powerpc: Add a schema for the 'sleep' property
  dt-bindings: pinctrl: sirf: Fix typo abitrary
  dt-bindings: pinctrl: qcom: Fix typo abitrary
  dt-bindings: Explicitly allow additional properties in common schemas
  dt-bindings: Use 'additionalProperties' instead of 'unevaluatedProperties'
  dt-bindings: Add missing 'unevaluatedProperties'
  Docs: Fixing spelling errors in Documentation/devicetree/bindings/
  dt-bindings: arm: hisilicon: convert Hi6220 domain controller bindings to json-schema
  dt-bindings: riscv: convert pwm bindings to json-schema
  dt-bindings: riscv: convert plic bindings to json-schema
  dt-bindings: fu540: prci: convert PRCI bindings to json-schema
  ...

1 files changed, 98 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
new file mode 100644
index 000000000000..3f4a1939554d
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2020 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive L2 Cache Controller
+
+maintainers:
+  - Sagar Kadam <sagar.kadam@sifive.com>
+  - Yash Shah <yash.shah@sifive.com>
+  - Paul Walmsley  <paul.walmsley@sifive.com>
+
+description:
+  The SiFive Level 2 Cache Controller is used to provide access to fast copies
+  of memory for masters in a Core Complex. The Level 2 Cache Controller also
+  acts as directory-based coherency manager.
+  All the properties in ePAPR/DeviceTree specification applies for this platform.
+
+allOf:
+  - $ref: /schemas/cache-controller.yaml#
+
+select:
+  properties:
+    compatible:
+      items:
+       - enum:
+          - sifive,fu540-c000-ccache
+
+  required:
+    - compatible
+
+properties:
+  compatible:
+    items:
+      - const: sifive,fu540-c000-ccache
+      - const: cache
+
+  cache-block-size:
+    const: 64
+
+  cache-level:
+    const: 2
+
+  cache-sets:
+    const: 1024
+
+  cache-size:
+    const: 2097152
+
+  cache-unified: true
+
+  interrupts:
+    description: |
+      Must contain entries for DirError, DataError and DataFail signals.
+    minItems: 3
+    maxItems: 3
+
+  reg:
+    maxItems: 1
+
+  next-level-cache: true
+
+  memory-region:
+    description: |
+      The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
+      The reserved memory node should be defined as per the bindings in reserved-memory.txt.
+
+additionalProperties: false
+
+required:
+  - compatible
+  - cache-block-size
+  - cache-level
+  - cache-sets
+  - cache-size
+  - cache-unified
+  - interrupts
+  - reg
+
+examples:
+  - |
+    cache-controller@2010000 {
+        compatible = "sifive,fu540-c000-ccache", "cache";
+        cache-block-size = <64>;
+        cache-level = <2>;
+        cache-sets = <1024>;
+        cache-size = <2097152>;
+        cache-unified;
+        reg = <0x2010000 0x1000>;
+        interrupt-parent = <&plic0>;
+        interrupts = <1>,
+                     <2>,
+                     <3>;
+        next-level-cache = <&L25>;
+        memory-region = <&l2_lim>;
+    };