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authorStuart Yoder <stuart.yoder@freescale.com>2013-03-06 02:39:08 +0400
committerKumar Gala <galak@kernel.crashing.org>2013-03-06 03:10:02 +0400
commit5986453b7fe495687e4eafad8a3dd1ffd106bc80 (patch)
tree4e3bd6dcd60b0d7b580380ca301c3cb0cc3bb454 /Documentation/devicetree/bindings/powerpc
parent54c9b2253d34e8998e4bff9ac2d7a3ba0b861d52 (diff)
downloadlinux-5986453b7fe495687e4eafad8a3dd1ffd106bc80.tar.xz
powerpc/e6500: Add architecture categories for e6500 cores
-also define a binding for fsl,eref-* properties Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'Documentation/devicetree/bindings/powerpc')
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+===================================================================
+Power Architecture CPU Binding
+Copyright 2013 Freescale Semiconductor Inc.
+
+Power Architecture CPUs in Freescale SOCs are represented in device trees as
+per the definition in ePAPR.
+
+In addition to the ePAPR definitions, the properties defined below may be
+present on CPU nodes.
+
+PROPERTIES
+
+ - fsl,eref-*
+ Usage: optional
+ Value type: <empty>
+ Definition: The EREF (EREF: A Programmer.s Reference Manual for
+ Freescale Power Architecture) defines the architecture for Freescale
+ Power CPUs. The EREF defines some architecture categories not defined
+ by the Power ISA. For these EREF-specific categories, the existence of
+ a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
+ name with all uppercase letters converted to lowercase, indicates that
+ the category is supported by the implementation.