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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2022-12-30 16:56:43 +0300 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-01-13 13:47:52 +0300 |
| commit | 12a18bb74f7500693bdfb6af2f99c05d2d43f9c6 (patch) | |
| tree | 9e612be24710c14820547df5cc4bfc71272f83ae /Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml | |
| parent | 45277153d46500ce7f4a1637412f0db7c208300a (diff) | |
| download | linux-12a18bb74f7500693bdfb6af2f99c05d2d43f9c6.tar.xz | |
dt-bindings: pinctrl: qcom: allow nine interrupts on SM6350
Almost all Qualcomm SoC Top Level Mode Multiplexers come with only
summary interrupt. SM6350 is different because downstream and upstream
DTS have nine of the interrupts. Allow such variation.
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml index 39f3ec5b7187..d95935fcc8b5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml @@ -22,7 +22,10 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + minItems: 9 + maxItems: 9 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true @@ -125,7 +128,16 @@ examples: pinctrl@f100000 { compatible = "qcom,sm6350-tlmm"; reg = <0x0f100000 0x300000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; #gpio-cells = <2>; interrupt-controller; |