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authorStephen Warren <swarren@nvidia.com>2012-04-04 19:27:47 +0400
committerLinus Walleij <linus.walleij@linaro.org>2012-04-18 15:53:11 +0400
commit7a865277fb0f9da9e456dfc11b0a564cbfc475cd (patch)
tree8d58cbf789afad362c4f467e2af876eaabe658fd /Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
parentc541adc637066407d4cda9db14dcb0e618966a4c (diff)
downloadlinux-7a865277fb0f9da9e456dfc11b0a564cbfc475cd.tar.xz
dt: pinctrl: Document device tree binding
The core pin controller bindings define: * The fact that pin controllers expose pin configurations as nodes in device tree. * That the bindings for those pin configuration nodes is defined by the individual pin controller drivers. * A standardized set of properties for client devices to define numbered or named pin configuration states, each referring to some number of the afore-mentioned pin configuration nodes. * That the bindings for the client devices determines the set of numbered or named states that must exist. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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