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author | Shawn Lin <shawn.lin@rock-chips.com> | 2016-09-01 10:44:53 +0300 |
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committer | Kishon Vijay Abraham I <kishon@ti.com> | 2016-09-10 14:18:32 +0300 |
commit | b11c821532b53976ff8af1b9c98d114facdfadcb (patch) | |
tree | 1abfff898183360e460a21ea888a45598dcd0777 /Documentation/devicetree/bindings/phy | |
parent | 0e08d2a727e68bbe426457dc61ec11a5c6a76ed6 (diff) | |
download | linux-b11c821532b53976ff8af1b9c98d114facdfadcb.tar.xz |
Documentation: bindings: add dt documentation for Rockchip PCIe PHY
This patch adds a binding that describes the Rockchip PCIe PHY found
on Rockchip SoCs PCIe interface.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r-- | Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt new file mode 100644 index 000000000000..0f6222a672ce --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt @@ -0,0 +1,31 @@ +Rockchip PCIE PHY +----------------------- + +Required properties: + - compatible: rockchip,rk3399-pcie-phy + - #phy-cells: must be 0 + - clocks: Must contain an entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must be "refclk" + - resets: Must contain an entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must be "phy" + +Example: + +grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + ... + + pcie_phy: pcie-phy { + compatible = "rockchip,rk3399-pcie-phy"; + #phy-cells = <0>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + resets = <&cru SRST_PCIEPHY>; + reset-names = "phy"; + }; +}; |