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| author | Kishon Vijay Abraham I <kishon@ti.com> | 2019-01-24 11:29:56 +0300 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2019-01-31 20:15:02 +0300 |
| commit | 1c5d2cc7196c8c45c02114858efa4dca69a86583 (patch) | |
| tree | 3e2445091fa5f1b8a4483a1e7eabec3454866b4f /Documentation/devicetree/bindings/pci | |
| parent | 33d5c207a9ed16e72f49b77b9387aea5a8a42219 (diff) | |
| download | linux-1c5d2cc7196c8c45c02114858efa4dca69a86583.tar.xz | |
dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7
Add syscon properties required for configuring PCIe in x2 lane mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/ti-pci.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index e03d23631f5b..d5cbfe6b0d89 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -13,6 +13,9 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", where <X> is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt + - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control + module and the register offset to specify lane + selection. HOST MODE ========= |