diff options
author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2021-07-28 14:51:58 +0300 |
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committer | David S. Miller <davem@davemloft.net> | 2021-07-28 15:38:53 +0300 |
commit | df11b8073e19bd0eedae630dae82f38eb374b80d (patch) | |
tree | 1e856b83102d1024536ac86306c441cd312fb298 /Documentation/devicetree/bindings/net | |
parent | 5d886947039d029f8ba1da6030c0a00ef330373d (diff) | |
download | linux-df11b8073e19bd0eedae630dae82f38eb374b80d.tar.xz |
dt-bindings: net: fsl,fec: add RGMII internal clock delay
Add RGMII internal clock delay for FEC controller.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/devicetree/bindings/net')
-rw-r--r-- | Documentation/devicetree/bindings/net/fsl,fec.yaml | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/net/fsl,fec.yaml b/Documentation/devicetree/bindings/net/fsl,fec.yaml index b14e0e7c1e42..eca41443fcce 100644 --- a/Documentation/devicetree/bindings/net/fsl,fec.yaml +++ b/Documentation/devicetree/bindings/net/fsl,fec.yaml @@ -96,6 +96,8 @@ properties: SOC internal PLL. The "enet_out"(option), output clock for external device, like supply clock for PHY. The clock is required if PHY clock source from SOC. + The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz. + The clock is required if SoC RGMII enable clock delay. clock-names: minItems: 2 @@ -107,6 +109,7 @@ properties: - ptp - enet_clk_ref - enet_out + - enet_2x_txclk phy-mode: true @@ -118,6 +121,12 @@ properties: mac-address: true + tx-internal-delay-ps: + enum: [0, 2000] + + rx-internal-delay-ps: + enum: [0, 2000] + phy-supply: description: Regulator that powers the Ethernet PHY. |