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authorJames Morris <james.l.morris@oracle.com>2014-01-06 15:23:01 +0400
committerJames Morris <james.l.morris@oracle.com>2014-01-06 15:23:01 +0400
commit38fd2c202a3d82bc12430bce5789fa2c2a406f71 (patch)
treea73513dbb015155f5236b391709b9083916b3136 /Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
parentdcf4e392867bf98d50ad108ed7c2bfb941e8c33d (diff)
parentd6e0a2dd12f4067a5bcefb8bbd8ddbeff800afbc (diff)
downloadlinux-38fd2c202a3d82bc12430bce5789fa2c2a406f71.tar.xz
Merge to v3.13-rc7 for prerequisite changes in the Xen code for TPM
Diffstat (limited to 'Documentation/devicetree/bindings/net/fsl-tsec-phy.txt')
-rw-r--r--Documentation/devicetree/bindings/net/fsl-tsec-phy.txt18
1 files changed, 17 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 2c6be0377f55..d2ea4605d078 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -86,6 +86,7 @@ General Properties:
Clock Properties:
+ - fsl,cksel Timer reference clock source.
- fsl,tclk-period Timer reference clock period in nanoseconds.
- fsl,tmr-prsc Prescaler, divides the output clock.
- fsl,tmr-add Frequency compensation value.
@@ -97,7 +98,7 @@ Clock Properties:
clock. You must choose these carefully for the clock to work right.
Here is how to figure good values:
- TimerOsc = system clock MHz
+ TimerOsc = selected reference clock MHz
tclk_period = desired clock period nanoseconds
NominalFreq = 1000 / tclk_period MHz
FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
@@ -114,6 +115,20 @@ Clock Properties:
Pulse Per Second (PPS) signal, since this will be offered to the PPS
subsystem to synchronize the Linux clock.
+ Reference clock source is determined by the value, which is holded
+ in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
+ value, which will be directly written in those bits, that is why,
+ according to reference manual, the next clock sources can be used:
+
+ <0> - external high precision timer reference clock (TSEC_TMR_CLK
+ input is used for this purpose);
+ <1> - eTSEC system clock;
+ <2> - eTSEC1 transmit clock;
+ <3> - RTC clock input.
+
+ When this attribute is not used, eTSEC system clock will serve as
+ IEEE 1588 timer reference clock.
+
Example:
ptp_clock@24E00 {
@@ -121,6 +136,7 @@ Example:
reg = <0x24E00 0xB0>;
interrupts = <12 0x8 13 0x8>;
interrupt-parent = < &ipic >;
+ fsl,cksel = <1>;
fsl,tclk-period = <10>;
fsl,tmr-prsc = <100>;
fsl,tmr-add = <0x999999A4>;