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authorSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2014-10-21 13:22:41 +0400
committerUlf Hansson <ulf.hansson@linaro.org>2014-11-10 14:40:47 +0300
commit0654bb3cdd5142ca8bf27a4f72bf22098394fbd5 (patch)
treeeb5e7a285482d40a10de56759855e13b60e96c0c /Documentation/devicetree/bindings/mmc
parent8afdc9cca27fc299ffe7b535b299adc03efab851 (diff)
downloadlinux-0654bb3cdd5142ca8bf27a4f72bf22098394fbd5.tar.xz
mmc: sdhci-pxav3: Document clocks and additional clock-names property
Now that sdhci-pxav3 driver allows to have more than one IP clock defined, document both clocks and clock-names properties. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mmc')
-rw-r--r--Documentation/devicetree/bindings/mmc/sdhci-pxa.txt7
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
index 86223c3eda90..4dd6deb90719 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
@@ -12,6 +12,10 @@ Required properties:
* for "marvell,armada-380-sdhci", two register areas. The first one
for the SDHCI registers themselves, and the second one for the
AXI/Mbus bridge registers of the SDHCI unit.
+- clocks: Array of clocks required for SDHCI; requires at least one for
+ I/O clock.
+- clock-names: Array of names corresponding to clocks property; shall be
+ "io" for I/O clock and "core" for optional core clock.
Optional properties:
- mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.
@@ -23,6 +27,8 @@ sdhci@d4280800 {
reg = <0xd4280800 0x800>;
bus-width = <8>;
interrupts = <27>;
+ clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
+ clock-names = "io", "core";
non-removable;
mrvl,clk-delay-cycles = <31>;
};
@@ -32,5 +38,6 @@ sdhci@d8000 {
reg = <0xd8000 0x1000>, <0xdc000 0x100>;
interrupts = <0 25 0x4>;
clocks = <&gateclk 17>;
+ clock-names = "io";
mrvl,clk-delay-cycles = <0x1F>;
};