diff options
| author | Andy Gross <agross@codeaurora.org> | 2015-02-10 01:01:07 +0300 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2015-04-03 23:33:43 +0300 |
| commit | a8b21018de2ec8864176670c87015b19babdfe58 (patch) | |
| tree | af730fc8e6ae9ca84f365f4929c0ab2ca30cef4f /Documentation/devicetree/bindings/mfd | |
| parent | 2d9ad4f85ed43101f55816472895e112203f9881 (diff) | |
| download | linux-a8b21018de2ec8864176670c87015b19babdfe58.tar.xz | |
mfd: qcom,tcsr: Add device tree binding for TCSR
This patch adds the device tree binding for the Qualcomm Top Control and
Status Register device. The TCSR is comprised of a set of registers that
provide various control and status functions for attached peripherals.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'Documentation/devicetree/bindings/mfd')
| -rw-r--r-- | Documentation/devicetree/bindings/mfd/qcom,tcsr.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt new file mode 100644 index 000000000000..e90519d566a3 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.txt @@ -0,0 +1,22 @@ +QCOM Top Control and Status Register + +Qualcomm devices have a set of registers that provide various control and status +functions for their peripherals. This node is intended to allow access to these +registers via syscon. + +Required properties: +- compatible: Should contain: + "qcom,tcsr-ipq8064", "syscon" for IPQ8064 + "qcom,tcsr-apq8064", "syscon" for APQ8064 + "qcom,tcsr-msm8660", "syscon" for MSM8660 + "qcom,tcsr-msm8960", "syscon" for MSM8960 + "qcom,tcsr-msm8974", "syscon" for MSM8974 + "qcom,tcsr-apq8084", "syscon" for APQ8084 + "qcom,tcsr-msm8916", "syscon" for MSM8916 +- reg: Address range for TCSR registers + +Example: + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-msm8960", "syscon"; + reg = <0x1a400000 0x100>; + }; |