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| author | Michal Simek <michal.simek@amd.com> | 2023-05-16 16:51:08 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-06-05 14:09:19 +0300 |
| commit | d5c421d24d7eca0a2c9708cf0b3fbc1e63f9136a (patch) | |
| tree | 3f00fd7526f58daf595fe62a57684ad0ff19237b /Documentation/devicetree/bindings/memory-controllers | |
| parent | 45fe0dc4ea2efff3eff4e54e31e679224c095c2a (diff) | |
| download | linux-d5c421d24d7eca0a2c9708cf0b3fbc1e63f9136a.tar.xz | |
dt-bindings: xilinx: Switch xilinx.com emails to amd.com
@xilinx.com is still working but better to switch to new amd.com after
AMD/Xilinx acquisition.
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Acked-by: Damien Le Moal <dlemoal@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f5b2bd1e78407e4128fc8f0b5874ba723e710a88.1684245058.git.michal.simek@amd.com
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
| -rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml index e68c4306025a..6b62d5d83476 100644 --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -9,7 +9,7 @@ title: Synopsys DesignWare Universal Multi-Protocol Memory Controller maintainers: - Krzysztof Kozlowski <krzk@kernel.org> - Manish Narani <manish.narani@xilinx.com> - - Michal Simek <michal.simek@xilinx.com> + - Michal Simek <michal.simek@amd.com> description: | Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml index 8f72e2f8588a..7864a1c994eb 100644 --- a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml @@ -9,7 +9,7 @@ title: Zynq A05 DDR Memory Controller maintainers: - Krzysztof Kozlowski <krzk@kernel.org> - Manish Narani <manish.narani@xilinx.com> - - Michal Simek <michal.simek@xilinx.com> + - Michal Simek <michal.simek@amd.com> description: The Zynq DDR ECC controller has an optional ECC support in half-bus width |