Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM Device-tree updates from Olof Johansson:
 "As usual, this is where the bulk of our changes end up landing each
  merge window.

  The individual updates are too many to enumerate, many many platforms
  have seen additions of device descriptions such that they are
  functionally more complete (in fact, this is often the bulk of updates
  we see).

  Instead I've mostly focused on highlighting the new platforms below as
  they are introduced. Sometimes the introduction is of mostly a
  fragment, that later gets filled in on later releases, and in some
  cases it's near-complete platform support. The latter is more common
  for derivative platforms that already has similar support in-tree.

  Two SoCs are slight outliers from the usual range of additions.
  Allwinner support for F1C100s, a quite old SoC (ARMv5-based) shipping
  in the Lychee Pi Nano platform. At the other end is NXP Layerscape
  LX2160A, a 16-core 2.2GHz Cortex-A72 SoC with a large amount of I/O
  aimed at infrastructure/networking.

  TI updates stick out in the diff stats too, in particular because they
  have moved the description of their L4 on-chip interconnect to
  devicetree, which opens up for removal of even more of their
  platform-specific 'hwmod' description tables over the next few
  releases.

  SoCs:
   - Qualcomm QCS404 (4x Cortex-A53)
   - Allwinner T3 (rebranded R40) and f1c100s (armv5)
   - NXP i.MX7ULP (1x Cortex-A7 + 1x Cortex-M4)
   - NXP LS1028A (2x Cortex-A72), LX2160A (16x Cortex-A72)

  New platforms:
   - Rockchip: Gru Scarlet (RK3188 Tablet)
   - Amlogic: Phicomm N1 (S905D), Libretech S805-AC
   - Broadcom: Linksys EA6500 v2 Wi-Fi router (BCM4708)
   - Qualcomm: QCS404 base platform and EVB
   - Qualcomm: Remove of Arrow SD600
   - PXA: First PXA3xx DT board: Raumfeld
   - Aspeed: Facebook Backpack-CMM BMC
   - Renesas iWave G20D-Q7 (RZ/G1N)
   - Allwinner t3-cqa3t-bv3 (T3/R40) and Lichee Pi Nano (F1C100s)
   - Allwinner Emlid Neutis N5, Mapleboard MP130
   - Marvell Macchiatobin Single Shot (Armada 8040, no 10GbE)
   - i.MX: mtrion emCON-MX6, imx6ul-pico-pi, imx7d-sdb-reva
   - VF610: Liebherr's BK4 device, ZII SCU4 AIB board
   - i.MX7D PICO Hobbit baseboard
   - i.MX7ULP EVK board
   - NXP LX2160AQDS and LX2160ARDB boards

  Other:
   - Coresight binding updates across the board
   - CPU cooling maps updates across the board"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (648 commits)
  ARM: dts: suniv: Fix improper bindings include patch
  ARM: dts: sunxi: Enable Broadcom-based Bluetooth for multiple boards
  arm64: dts: allwinner: a64: bananapi-m64: Add Bluetooth device node
  ARM: dts: suniv: Fix improper bindings include patch
  arm64: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller
  arm64: dts: Remove unused properties from FSL QSPI driver nodes
  ARM: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller
  ARM: dts: imx6sx-sdb: Fix the reg properties for the FSL QSPI nodes
  ARM: dts: Remove unused properties from FSL QSPI driver nodes
  arm64: dts: ti: k3-am654: Enable main domain McSPI0
  arm64: dts: ti: k3-am654: Add McSPI DT nodes
  arm64: dts: ti: k3-am654: Populate power-domain property for UART nodes
  arm64: dts: ti: k3-am654-base-board: Enable ECAP PWM
  arm64: dts: ti: k3-am65-main: Add ECAP PWM node
  arm64: dts: ti: k3-am654-base-board: Add I2C nodes
  arm64: dts: ti: am654-base-board: Add pinmux for main uart0
  arm64: dts: ti: k3-am65: Add pinctrl regions
  dt-bindings: pinctrl: k3: Introduce pinmux definitions
  ARM: dts: exynos: Specify I2S assigned clocks in proper node
  ARM: dts: exynos: Add missing CPUs in cooling maps for Odroid X2
  ...

1 files changed, 104 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
new file mode 100644
index 000000000000..add95367640b
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
@@ -0,0 +1,104 @@
+Embedded Memory Controller
+
+Properties:
+- name : Should be emc
+- #address-cells : Should be 1
+- #size-cells : Should be 0
+- compatible : Should contain "nvidia,tegra20-emc".
+- reg : Offset and length of the register set for the device
+- nvidia,use-ram-code : If present, the sub-nodes will be addressed
+  and chosen using the ramcode board selector. If omitted, only one
+  set of tables can be present and said tables will be used
+  irrespective of ram-code configuration.
+- interrupts : Should contain EMC General interrupt.
+- clocks : Should contain EMC clock.
+
+Child device nodes describe the memory settings for different configurations and clock rates.
+
+Example:
+
+	memory-controller@7000f400 {
+		#address-cells = < 1 >;
+		#size-cells = < 0 >;
+		compatible = "nvidia,tegra20-emc";
+		reg = <0x7000f4000 0x200>;
+		interrupts = <0 78 0x04>;
+		clocks = <&tegra_car TEGRA20_CLK_EMC>;
+	}
+
+
+Embedded Memory Controller ram-code table
+
+If the emc node has the nvidia,use-ram-code property present, then the
+next level of nodes below the emc table are used to specify which settings
+apply for which ram-code settings.
+
+If the emc node lacks the nvidia,use-ram-code property, this level is omitted
+and the tables are stored directly under the emc node (see below).
+
+Properties:
+
+- name : Should be emc-tables
+- nvidia,ram-code : the binary representation of the ram-code board strappings
+  for which this node (and children) are valid.
+
+
+
+Embedded Memory Controller configuration table
+
+This is a table containing the EMC register settings for the various
+operating speeds of the memory controller. They are always located as
+subnodes of the emc controller node.
+
+There are two ways of specifying which tables to use:
+
+* The simplest is if there is just one set of tables in the device tree,
+  and they will always be used (based on which frequency is used).
+  This is the preferred method, especially when firmware can fill in
+  this information based on the specific system information and just
+  pass it on to the kernel.
+
+* The slightly more complex one is when more than one memory configuration
+  might exist on the system.  The Tegra20 platform handles this during
+  early boot by selecting one out of possible 4 memory settings based
+  on a 2-pin "ram code" bootstrap setting on the board. The values of
+  these strappings can be read through a register in the SoC, and thus
+  used to select which tables to use.
+
+Properties:
+- name : Should be emc-table
+- compatible : Should contain "nvidia,tegra20-emc-table".
+- reg : either an opaque enumerator to tell different tables apart, or
+  the valid frequency for which the table should be used (in kHz).
+- clock-frequency : the clock frequency for the EMC at which this
+  table should be used (in kHz).
+- nvidia,emc-registers : a 46 word array of EMC registers to be programmed
+  for operation at the 'clock-frequency' setting.
+  The order and contents of the registers are:
+    RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT,
+    WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR,
+    PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW,
+    TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE,
+    ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE,
+    ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0,
+    CFG_CLKTRIM_1, CFG_CLKTRIM_2
+
+		emc-table@166000 {
+			reg = <166000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 166000 >;
+			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+						 0 0 0 0 >;
+		};
+
+		emc-table@333000 {
+			reg = <333000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 333000 >;
+			nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+						 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+						 0 0 0 0 >;
+		};