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authorPunnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>2014-11-27 18:17:33 +0300
committerMichal Simek <michal.simek@xilinx.com>2015-07-31 11:50:05 +0300
commit1837649fd350bf25e20d05dbdd4449160ad0219b (patch)
treef45fa7965b0d2d1cf04e59272c85f260150543d9 /Documentation/devicetree/bindings/memory-controllers
parent6835fe4846756deb7ca7447fb7bdba6ecb21bd30 (diff)
downloadlinux-1837649fd350bf25e20d05dbdd4449160ad0219b.tar.xz
Documentation: devicetree: Add ECC information to synopsys ddr controller
Add ECC information to synopsys ddr memory controller. Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/synopsys.txt4
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
index f9c6454146b6..a43d26d41e04 100644
--- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
@@ -1,5 +1,9 @@
Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
+This controller has an optional ECC support in half-bus width (16-bit)
+configuration. The ECC controller corrects one bit error and detects
+two bit errors.
+
Required properties:
- compatible: Should be 'xlnx,zynq-ddrc-a05'
- reg: Base address and size of the controllers memory area