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| author | Joel Stanley <joel@jms.id.au> | 2017-10-31 05:12:03 +0300 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2017-12-02 13:41:15 +0300 |
| commit | edf7550a1f93a88be2bf743b5d352b278d1b789c (patch) | |
| tree | 518f1a1e87a87244af5697d97a3666eb7f6bfe9b /Documentation/devicetree/bindings/iio | |
| parent | 02c5dff52b3e1eb38513699e17cdf973a5a40322 (diff) | |
| download | linux-edf7550a1f93a88be2bf743b5d352b278d1b789c.tar.xz | |
iio: adc: aspeed: Deassert reset in probe
The ASPEED SoC must deassert a reset in order to use the ADC peripheral.
The device tree bindings are updated to document the resets phandle, and
the example is updated to match what is expected for both the reset and
clock phandle. Note that the bindings should have always had the reset
controller, as the hardware is unusable without it.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'Documentation/devicetree/bindings/iio')
| -rw-r--r-- | Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt index 674e133b7cd7..034fc2ba100e 100644 --- a/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt @@ -8,6 +8,7 @@ Required properties: - reg: memory window mapping address and length - clocks: Input clock used to derive the sample clock. Expected to be the SoC's APB clock. +- resets: Reset controller phandle - #io-channel-cells: Must be set to <1> to indicate channels are selected by index. @@ -15,6 +16,7 @@ Example: adc@1e6e9000 { compatible = "aspeed,ast2400-adc"; reg = <0x1e6e9000 0xb0>; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_ADC>; #io-channel-cells = <1>; }; |