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authorPaul Walmsley <paul@pwsan.com>2015-01-31 01:11:04 +0300
committerRob Herring <robh@kernel.org>2015-02-04 05:37:31 +0300
commit193c9d23a0f0b8ae0c2aeb517c953ba8aee4ceb9 (patch)
tree9508950b34a6f7723da6f9a3488897de99306583 /Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
parent2d4c0aef0ff4d4374590d6c7b259a259bb2cb21b (diff)
downloadlinux-193c9d23a0f0b8ae0c2aeb517c953ba8aee4ceb9.tar.xz
Documentation: DT bindings: add more Tegra chip compatible strings
Align compatible strings for several IP blocks present on Tegra chips with the latest doctrine from the DT maintainers: http://marc.info/?l=devicetree&m=142255654213019&w=2 The primary objective here is to avoid checkpatch warnings, per: http://marc.info/?l=linux-tegra&m=142201349727836&w=2 DT binding text files have been updated for the following IP blocks: - PCIe - SOR - SoC timers - AHB "gizmo" - APB_MISC - pinmux control - UART - PWM - I2C - SPI - RTC - PMC - eFuse - AHCI - HDA - XUSB_PADCTRL - SDHCI - SOC_THERM - AHUB - I2S - EHCI - USB PHY N.B. The nvidia,tegra20-timer compatible string is removed from the nvidia,tegra30-timer.txt documentation file because it's already mentioned in the nvidia,tegra20-timer.txt documentation file. This second version takes into account the following requests from Rob Herring <robherring2@gmail.com>: - Per-IP block patches have been combined into a single patch - Explicit documentation about which compatible strings are actually matched by the driver has been removed. In its place is implicit documentation that loosely follows Rob's prescribed format: "Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ..." [...] "You should attempt to document known values of <chip> if you use it" Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Dylan Reid <dgreid@chromium.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Jingchang Lu <jingchang.lu@freescale.com> Cc: John Crispin <blogic@openwrt.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mikko Perttunen <mperttunen@nvidia.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Peter Hurley <peter@hurleysoftware.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Takashi Iwai <tiwai@suse.de> Cc: Tejun Heo <tj@kernel.org> Cc: "Terje Bergström" <tbergstrom@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Zhang Rui <rui.zhang@intel.com> Cc: dri-devel@lists.freedesktop.org Cc: linux-i2c@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-pwm@vger.kernel.org Cc: linux-tegra@vger.kernel.org Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt')
-rw-r--r--Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt10
1 files changed, 5 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
index d8c98c7614d0..23e1d3194174 100644
--- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
+++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
@@ -1,11 +1,11 @@
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
Required properties:
-- compatible : should be:
- "nvidia,tegra20-efuse"
- "nvidia,tegra30-efuse"
- "nvidia,tegra114-efuse"
- "nvidia,tegra124-efuse"
+- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
+ must contain "nvidia,tegra30-efuse". For Tegra114, must contain
+ "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
+ Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where
+ <chip> is tegra132.
Details:
nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
due to a hardware bug. Tegra20 also lacks certain information which is