summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/dma/k3dma.txt
diff options
context:
space:
mode:
authorZhangfei Gao <zhangfei.gao@linaro.org>2013-08-27 06:20:10 +0400
committerVinod Koul <vinod.koul@intel.com>2013-08-28 09:53:40 +0400
commit8e6152bc660e69f526c6bf163ff0ebfdab90f6cf (patch)
tree18d27ff4cedae2a166ee0b780da0960b0696d533 /Documentation/devicetree/bindings/dma/k3dma.txt
parent0429936697321612e3c2edbfa2161856e737ac09 (diff)
downloadlinux-8e6152bc660e69f526c6bf163ff0ebfdab90f6cf.tar.xz
dmaengine: Add hisilicon k3 DMA engine driver
Add dmaengine driver for hisilicon k3 platform based on virt_dma Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Kai Yang <jean.yangkai@huawei.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'Documentation/devicetree/bindings/dma/k3dma.txt')
-rw-r--r--Documentation/devicetree/bindings/dma/k3dma.txt46
1 files changed, 46 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/dma/k3dma.txt b/Documentation/devicetree/bindings/dma/k3dma.txt
new file mode 100644
index 000000000000..23f8d712c3ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/k3dma.txt
@@ -0,0 +1,46 @@
+* Hisilicon K3 DMA controller
+
+See dma.txt first
+
+Required properties:
+- compatible: Should be "hisilicon,k3-dma-1.0"
+- reg: Should contain DMA registers location and length.
+- interrupts: Should contain one interrupt shared by all channel
+- #dma-cells: see dma.txt, should be 1, para number
+- dma-channels: physical channels supported
+- dma-requests: virtual channels supported, each virtual channel
+ have specific request line
+- clocks: clock required
+
+Example:
+
+Controller:
+ dma0: dma@fcd02000 {
+ compatible = "hisilicon,k3-dma-1.0";
+ reg = <0xfcd02000 0x1000>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ dma-requests = <27>;
+ interrupts = <0 12 4>;
+ clocks = <&pclk>;
+ status = "disable";
+ };
+
+Client:
+Use specific request line passing from dmax
+For example, i2c0 read channel request line is 18, while write channel use 19
+
+ i2c0: i2c@fcb08000 {
+ compatible = "snps,designware-i2c";
+ dmas = <&dma0 18 /* read channel */
+ &dma0 19>; /* write channel */
+ dma-names = "rx", "tx";
+ };
+
+ i2c1: i2c@fcb09000 {
+ compatible = "snps,designware-i2c";
+ dmas = <&dma0 20 /* read channel */
+ &dma0 21>; /* write channel */
+ dma-names = "rx", "tx";
+ };
+