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| author | Archit Taneja <architt@codeaurora.org> | 2018-01-17 12:34:47 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2018-02-20 18:41:21 +0300 |
| commit | 31767e00e428c891343f94e5a94909bb7a642bcf (patch) | |
| tree | 07a2fd8fad72d22f8f977d24445fd11c6317a0a9 /Documentation/devicetree/bindings/display | |
| parent | 8c4905fd4939c59e0f7993ba34883e328eef4b59 (diff) | |
| download | linux-31767e00e428c891343f94e5a94909bb7a642bcf.tar.xz | |
dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096).
>From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required,
but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names
each PHY revision needs.
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'Documentation/devicetree/bindings/display')
| -rw-r--r-- | Documentation/devicetree/bindings/display/msm/dsi.txt | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 9c3ad6bbb9f0..26a1796b7145 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY and PHY - regulator + * "qcom,dsi-phy-14nm" +- reg: Physical base address and length of the registers of PLL, PHY. Some + revisions require the PHY regulator base address, whereas others require the + PHY lane base address. See below for each PHY revision. - reg-names: The names of register regions. The following regions are required: + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" + For DSI 14nm PHY: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_lane" - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1). - power-domains: Should be <&mmcc MDSS_GDSC>. @@ -103,6 +110,8 @@ Required properties: For 20nm PHY: - vddio-supply: phandle to vdd-io regulator device node - vcca-supply: phandle to vcca regulator device node + For 14nm PHY: +- vcca-supply: phandle to vcca regulator device node Optional properties: - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY |