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author | James Morris <jmorris@namei.org> | 2011-11-16 05:39:48 +0400 |
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committer | James Morris <jmorris@namei.org> | 2011-11-16 05:39:48 +0400 |
commit | 24942c8e5cc8696064ee207ff29d4cf21f70dafc (patch) | |
tree | 08a8221eb72ec3da7746d7d76f6f5915ce77cde7 /Documentation/devicetree/bindings/crypto/picochip-spacc.txt | |
parent | e163bc8e4a0cd1cdffadb58253f7651201722d56 (diff) | |
parent | ff0ff78068dd8a962358dbbdafa9d6f24540d3e5 (diff) | |
download | linux-24942c8e5cc8696064ee207ff29d4cf21f70dafc.tar.xz |
Merge branch 'master'; commit 'v3.2-rc2' into next
Diffstat (limited to 'Documentation/devicetree/bindings/crypto/picochip-spacc.txt')
-rw-r--r-- | Documentation/devicetree/bindings/crypto/picochip-spacc.txt | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt new file mode 100644 index 000000000000..d8609ece1f4c --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt @@ -0,0 +1,23 @@ +Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings + +Picochip picoXcell devices contain crypto offload engines that may be used for +IPSEC and femtocell layer 2 ciphering. + +Required properties: + - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine + "picochip,spacc-l2" for the femtocell layer 2 ciphering engine. + - reg : Offset and length of the register set for this device + - interrupt-parent : The interrupt controller that controls the SPAcc + interrupt. + - interrupts : The interrupt line from the SPAcc. + - ref-clock : The input clock that drives the SPAcc. + +Example SPAcc node: + +spacc@10000 { + compatible = "picochip,spacc-ipsec"; + reg = <0x100000 0x10000>; + interrupt-parent = <&vic0>; + interrupts = <24>; + ref-clock = <&ipsec_clk>, "ref"; +}; |