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authorJames Morris <jmorris@namei.org>2011-11-16 05:39:48 +0400
committerJames Morris <jmorris@namei.org>2011-11-16 05:39:48 +0400
commit24942c8e5cc8696064ee207ff29d4cf21f70dafc (patch)
tree08a8221eb72ec3da7746d7d76f6f5915ce77cde7 /Documentation/devicetree/bindings/crypto/picochip-spacc.txt
parente163bc8e4a0cd1cdffadb58253f7651201722d56 (diff)
parentff0ff78068dd8a962358dbbdafa9d6f24540d3e5 (diff)
downloadlinux-24942c8e5cc8696064ee207ff29d4cf21f70dafc.tar.xz
Merge branch 'master'; commit 'v3.2-rc2' into next
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+Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
+
+Picochip picoXcell devices contain crypto offload engines that may be used for
+IPSEC and femtocell layer 2 ciphering.
+
+Required properties:
+ - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
+ "picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
+ - reg : Offset and length of the register set for this device
+ - interrupt-parent : The interrupt controller that controls the SPAcc
+ interrupt.
+ - interrupts : The interrupt line from the SPAcc.
+ - ref-clock : The input clock that drives the SPAcc.
+
+Example SPAcc node:
+
+spacc@10000 {
+ compatible = "picochip,spacc-ipsec";
+ reg = <0x100000 0x10000>;
+ interrupt-parent = <&vic0>;
+ interrupts = <24>;
+ ref-clock = <&ipsec_clk>, "ref";
+};